INJECTION-LOCKED OSCILLATOR AND METHOD FOR CONTROLLING JITTER AND/OR PHASE NOISE

• US 20170040941A1
• Filed: 07/28/2016
• Published: 02/09/2017
• Est. Priority Date: 08/06/2015
• Status: Active Grant

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: CHATWIN, JEREMY
• Granted Patent: US 9,755,574 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H03B 1/04 Reducing undesired oscillations, e.g. harmonics
• CPC Class Codes: H03B 2200/009 Reduction of phase noise
• CPC Class Codes: H03K 3/013 Modifications of generator to prevent operation by noise or interference
• CPC Class Codes: H03K 3/0315 Ring oscillators
• CPC Class Codes: H03K 3/0322 with differential cells
• CPC Class Codes: H03K 3/356121 with synchronous operation H03K3/35613, H03K3/356147 take precedence
• CPC Class Codes: H03L 7/24 using a reference signal directly applied to the generator

Abstract

Various aspects of an injection-locked oscillator and method for controlling jitter and/or phase noise are disclosed herein. In accordance with an embodiment, an injection-locked oscillator includes one or more circuits that are configured to receive a pair of complementary phase output signals from one or more gain stages of the injection-locked oscillator. The one or more circuits may be configured to receive one or more switching signals. The received pair of complementary phase output signals are shorted by use of the one or more received switching signals. The shorting reduces the phase difference between an input signal and an output signal of the injection-locked oscillator.

Claims

1. An injection-locked oscillator, comprising:

one or more circuits configured to;

receive a pair of complementary phase output signals from one or more gain stages of said injection-locked oscillator;

receive one or more switching signals; and

short said received pair of complementary phase output signals, utilizing one or more said received switching signals, wherein said shorting reduces phase difference between an input signal and an output signal of said injection-locked oscillator.

2. The injection-locked oscillator according to claim 1, wherein said one or more gain stages of said injection-locked oscillator comprises at least one inverter or current mode logic (CML)-based circuitry.

3. The injection-locked oscillator according to claim 2, wherein said inverter is a complementary metal-oxide semiconductor (CMOS) based inverter or a current starved inverter.

4. The injection-locked oscillator according to claim 1, wherein said one or more circuits comprise one or more shorting switches for enabling said shorting of said received pair of complementary phase output signals.

5. The injection-locked oscillator according to claim 4, wherein said one or more shorting switches comprises one of:

a N-type metal-oxide-semiconductor (NMOS) transistor or a P-type metal-oxide-semiconductor (PMOS) transistor for said shorting of said received pair of complementary phase output signals.

6. The injection-locked oscillator according to claim 5, wherein said one or more shorting switches comprises said NMOS transistor and said PMOS transistor arranged in parallel configuration.

7. The injection-locked oscillator according to claim 4, wherein said one or more switching signals correspond to one or more shorting pulses applied periodically to said one or more shorting switches for said shorting, wherein a duration of said shorting is prefixed or configurable.

8. The injection-locked oscillator according to claim 4, wherein a number of shorting switches, which are enabled to receive said one or more shorting pulses, is dependent on a target injection strength to be achieved by said injection-locked oscillator.

9. The injection-locked oscillator according to claim 1, further comprises a plurality of gain stages arranged such that a pair of complementary phase output signals from one gain stage is coupled to a pair of input signals of a subsequent gain stage.

10. The injection-locked oscillator according to claim 1, wherein a rising transition of said pair of complementary phase output signals of one gain stage leads another pair of complementary phase output signals of a subsequent gain stage.

11. The injection-locked oscillator according to claim 1, wherein a rising edge of said pair of complementary phase output signals is injection locked for a particular time period to said incoming signal phase by said shorting.

12. The injection-locked oscillator according to claim 1, wherein a falling edge of said pair of complementary phase output signals is injection locked for a particular time period to said incoming signal phase by said shorting.

13. The injection-locked oscillator according to claim 1, further comprises a resonator to adjust said output signal phase of said injection-locked oscillator for said reduction in said phase difference.

20. The method according to claim 1, further comprising adjusting said output signal phase of said injection-locked oscillator for said reduction in said phase difference by use of a resonator in said injection-locked oscillator.

14. A method for reducing jitter, said method comprising:

receiving, by one or more circuits of an injection-locked oscillator, a pair of complementary phase output signals from one or more gain stages of said injection-locked oscillator;

receiving, by said one or more circuits, one or more switching signals; and

shorting, by said one or more circuits, said received pair of complementary phase output signals to reduce phase difference between an input signal and an output signal of said injection-locked oscillator.

15. The method according to claim 14, wherein said one or more gain stages of said injection-locked oscillator comprises at least one inverter or current mode logic (CML)-based circuitry.

16. The method according to claim 14, wherein said one or more switching signals correspond to one or more shorting pulses applied periodically to one or more shorting switches of said injection-locked oscillator for said shorting, wherein a duration of said shorting is prefixed or configurable.

17. The method according to claim 14, wherein a rising transition of said pair of complementary phase output signals of one gain stage leads another pair of complementary phase output signals of a subsequent gain stage.

18. The method according to claim 14, wherein a rising edge of said pair of complementary phase output signals is injection locked for a particular time period to said incoming signal phase by said shorting.

19. The method according to claim 14, wherein a falling edge of said pair of complementary phase output signals is injection locked for a particular time period to said incoming signal phase by said shorting.