INTEGRATED CIRCUIT CONTROL OF ANTI-SERIES SWITCHES

• US 20170040993A1
• Filed: 08/07/2015
• Published: 02/09/2017
• Est. Priority Date: 08/07/2015
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: JANSSENS, Johan Camiel Julia
• Granted Patent: US 10,122,359 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H03K 17/6874 in a symmetrical configuration
• CPC Class Codes: H03K 19/1732 by limitation or reduction of the pin/gate ratio for data-processing equipment G06F1/22

Abstract

An integrated circuit controls one or more external back-to-back (anti-series) transistor switches with three pins per switch. Two pins couple the switch terminals of the external switch to terminals of an internal anti-series switch. An intermediate source node of the internal switch provides a reference voltage that is representative of the external switch'"'"'s intermediate source node. A predriver of the integrated circuit drives a gate signal relative to the reference voltage, enabling fast, non-dissipative switching of the external switch. A disclosed method includes coupling switch terminal signals from an external anti-series switch to terminals of an internal anti-series switch; and driving a gate signal to the external anti-series switch relative to a reference voltage of an intermediate node of the internal anti-series switch.

Claims

1. An integrated circuit comprising:

a gate pin that couples to a shared gate node of two source-connected transistors forming an external anti-series switch between two switch terminals, the external anti-series switch having an external intermediate node that lacks a dedicated pin from the integrated circuit;

two terminal pins that couple to the two switch terminals;

an internal anti-series switch including two integrated transistors between the two terminal pins, the two integrated transistors having an internal intermediate node that connects their sources, the internal intermediate node providing a reference voltage; and

a controller with a predriver that drives the gate pin relative to the reference voltage.

2. The integrated circuit of claim 1, wherein the two integrated transistors are matched to each other.

3. The integrated circuit of claim 1, wherein the two integrated transistors have a shared gate terminal coupled to the gate pin.

4. The integrated circuit of claim 1, wherein the two integrated transistors have a shared gate node driven by the controller separately from the gate pin.

5. The integrated circuit of claim 1, wherein each of the two integrated transistors have a respective gate driven by a respective gate signal from the controller.

6. The integrated circuit of claim 1, wherein a buffered version of the reference voltage serves as local ground for the predriver.

7. The integrated circuit of claim 1, wherein the predriver receives as a local ground a level-shifted version of the reference voltage.

8. The integrated circuit of claim 1, wherein the controller asserts and de-asserts the gate pin based at least in part on voltages of the two terminal pins.

9. The integrated circuit of claim 1, wherein the controller asserts and de-asserts the gate pin based at least in part on the reference voltage.

10. The integrated circuit of claim 1, wherein the two integrated transistors have a lower gate breakdown voltage than the two source-connected transistors of the external anti-series switch.

11. The integrated circuit of claim 1, wherein the gate pin and two terminal pins form one set of pins for driving an external anti-series switch, and wherein the integrated circuit comprises multiple such sets of pins, each set for driving an external anti-series switch.

12. The integrated circuit of claim 11, wherein the integrated circuit comprises for each set of pins a corresponding internal anti-series switch.

13. A method for controlling an external anti-series switch having an external intermediate node, said controlling employing an integrated circuit that forgoes direct access to the external intermediate node, the method comprising:

coupling switch terminal signals from the external anti-series switch to terminals of an internal anti-series switch of the integrated circuit; and

driving a gate signal to the external anti-series switch relative to a reference voltage of an intermediate node of the internal anti-series switch.

14. The method of claim 13, further comprising coupling the gate signal to a shared gate of integrated transistors forming the internal anti-series switch.

15. The method of claim 13, further comprising driving gates of the integrated transistors forming the internal anti-series switch separately from the gate signal to the external anti-series switch.

16. The method of claim 13, further comprising deriving a local ground for a predriver supplying the gate signal from a level-shifted version of the reference voltage.

17. The method of claim 13, further comprising buffering the reference voltage as a local ground for a predriver supplying the gate signal.

18. The method of claim 13, further comprising employing multiple internal anti-series switches to provide reference voltages representing intermediate node voltages of corresponding external anti-series switches.

19. The method of claim 18, wherein each intermediate node for the internal and external anti-series switches is a shared source node.

20. The method of claim 13, wherein said driving includes asserting and de-asserting the gate signal based at least in part on the reference voltage.