POWER EFFICIENT FETCH ADAPTATION

• US 20170046159A1
• Filed: 08/14/2015
• Published: 02/16/2017
• Est. Priority Date: 08/14/2015
• Status: Active Application

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: PRIYADARSHI, Shivam, AL SHEIKH, Rami Mohammad, DAMODARAN, Raguram
• Application Number:
  US14/827,262
• Publication Number:
  US 20170046159A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 2212/452 Instruction code
• CPC Class Codes: G06F 9/3802 Instruction prefetching
• CPC Class Codes: G06F 9/3804 for branches, e.g. hedging, branch folding
• CPC Class Codes: G06F 9/3844 using dynamic branch prediction, e.g. using branch history tables

Abstract

Systems and methods relate to an instruction fetch unit of a processor, such as a superscalar processor. The instruction fetch unit includes a fetch bandwidth predictor (FBWP) configured to predict a number of instructions to be fetched in a fetch group of instructions in a pipeline stage of the processor. A first entry of the FBWP corresponding to the fetch group corresponds to a prediction of the number of instructions to be fetched, based on occurrence and location of a predicted taken branch instruction in the fetch group and a confidence level associated with the predicted number in the prediction field. The instruction fetch unit is configured to fetch only the predicted number of instructions, rather than the maximum number of entries that can be fetched in the pipeline stage, if the confidence level is greater than a predetermined threshold. In this manner, wasteful fetching of instructions is avoided.

Claims

1. A method of fetching instructions for a processor, the method comprising;

predicting a number of instructions to be fetched in a first fetch group of instructions, based at least in part on occurrence and location of a predicted taken branch instruction in the first fetch group;

determining if a confidence level associated with the predicted number of instructions is greater than a predetermined threshold; and

fetching the predicted number of instructions in a pipeline stage of the processor if the confidence level is greater than the predetermined threshold.

2. The method of claim 1, wherein the predicted number of instructions is less than the maximum number of instructions that can be fetched in the pipeline stage.

3. The method of claim 1, comprising fetching the predicted number of instructions from an instruction cache associated with the processor.

4. The method of claim 1, wherein the predicted taken branch instruction is an instruction predicted to change control flow of one or more instructions in the first fetch group.

5. The method of claim 1, comprising determining the occurrence and location of the predicted taken branch instruction in the first fetch group from a table comprising information regarding occurrence and location of predicted taken branch instructions in fetch groups.

6. The method of claim 5, wherein the information for the first fetch group is stored in a first entry of the table.

7. The method of claim 6, comprising accessing the first entry based on an address of a first instruction of the first fetch group and a history of branch instructions.

8. The method of claim 6, wherein the information for the first fetch group stored in the first entry comprises an indication of whether the first entry is valid, a confidence level, and a location of the predicted taken branch instruction in the first fetch group.

9. The method of claim 8, comprising training the first entry by increasing or decreasing the confidence level based on whether the predicted number of instructions is correct or incorrect, respectively.

10. The method of claim 9, comprising determining that the predicted number of instructions is incorrect when the predicted number comprises an over-prediction, wherein the predicted taken branch instruction in the first fetch group is located within a smaller number of instructions in the first fetch group than the predicted number of instructions.

11. The method of claim 10 comprising updating the location of the predicted taken branch instruction in the first entry to indicate the smaller number of instructions in the first fetch group.

12. The method of claim 9, comprising determining that the predicted number is incorrect when the predicted number comprises an under-prediction, wherein the predicted taken branch instruction is not located within the first fetch group.

13. The method of claim 12 further comprising determining that the predicted taken branch instruction is located in a second fetch group and updating the location of the predicted taken branch instruction in the first entry corresponding to the first fetch group based on the predicted number of instructions for the first fetch group and the location of the predicted taken branch instruction in the second fetch group.

14. The method of claim 12 further comprising determining either that the location of the predicted taken branch instruction in the second fetch group is beyond a location that can be fetched in the first fetch group, or the second fetch group does not contain a predicted taken branch instruction, and updating the location of the predicted taken branch instruction in the first entry to indicate the maximum number of instructions that can be fetched in the first fetch group.

15. An instruction fetch unit for a processor, the instruction fetch unit comprising:

a fetch bandwidth predictor (FBWP) configured to predict a number of instructions to be fetched in a first fetch group of instructions in a pipeline stage of the processor, wherein a first entry of the FBWP corresponding to the first fetch group comprises;

a prediction field comprising a prediction of the number of instructions to be fetched, based at least in part on occurrence and location of a predicted taken branch instruction in the first fetch group; and

a confidence level associated with the predicted number in the prediction field;

wherein the instruction fetch unit is configured to fetch the predicted number of instructions in the pipeline stage if the confidence level is greater than a predetermined threshold.

16. The instruction fetch unit of claim 15, wherein the predicted number of instructions is less than the maximum number of instructions that can be fetched in the pipeline stage.

17. The instruction fetch unit of claim 15, wherein the first entry of the FBWP is accessed based on a function of an instruction address of a first instruction of the first fetch group and history of prior branch instructions.

18. The instruction fetch unit of claim 17, wherein the FBWP comprises hash logic to implement the function.

19. The instruction fetch unit of claim 15, wherein the FBWP comprises a confidence counter to indicate the confidence level, wherein the confidence counter is incremented or decremented based on whether the predicted number in the prediction field is correct or incorrect respectively.

20. The instruction fetch unit of claim 19, wherein the predicted number is incorrect when the predicted number comprises an over-prediction, wherein the predicted taken branch instruction is located within a smaller number of instructions in the first fetch group than the predicted number.

21. The instruction fetch unit of claim 19, wherein the predicted number is incorrect when the predicted number comprises an under-prediction, wherein the predicted taken branch instruction is not located within the first fetch group.

22. The instruction fetch unit of claim 15, wherein the processor is a superscalar processor.

23. The instruction fetch unit of claim 15 integrated into a device selected from the group consisting of a set top box, music player, video player, entertainment unit, navigation device, communications device, personal digital assistant (PDA), fixed location data unit, and a computer.

24. A system comprising:

means for predicting a number of instructions to be fetched in a first fetch group of instructions, based at least in part on occurrence and location of a predicted taken branch instruction in the first fetch group of instructions;

means for determining if a confidence level associated with the predicted number of instructions is greater than a predetermined threshold; and

means for fetching the predicted number of instructions in a pipeline stage of a processor if the confidence level is greater than the predetermined threshold.

25. The system of claim 24, wherein the predicted number of instructions is less than the maximum number of instructions that can be fetched in the pipeline stage.

26. A non-transitory computer-readable storage medium comprising code, which, when executed by a processor, causes the processor to perform operations for fetching instructions, the non-transitory computer-readable storage medium comprising:

code for predicting a number of instructions to be fetched in a first fetch group of instructions, based at least in part on occurrence and location of a predicted taken branch instruction in the first fetch group;

code for determining if a confidence level associated with the predicted number of instructions is greater than a predetermined threshold; and

code for fetching the predicted number of instructions from an instruction cache if the confidence level is greater than the predetermined threshold.

27. The non-transitory computer-readable storage medium of claim 26, wherein the predicted number of instructions is less than the maximum number of instructions that can be fetched in a pipeline stage.

28. The non-transitory computer-readable storage medium of claim 26, comprising code for determining the occurrence and location of the predicted taken branch instruction in the first fetch group from a table comprising information regarding occurrence and location of predicted taken branch instructions in fetch groups.

29. The non-transitory computer-readable storage medium of claim 28, comprising code for accessing a first entry of the table comprising information regarding occurrence and location of predicted taken branch instructions in the first fetch group, based on an address of a first instruction of the first fetch group and a history of branch instructions.

30. The non-transitory computer-readable storage medium of claim 29, comprising code for training the first entry by increasing or decreasing the confidence level based on whether the predicted number of instructions is correct or incorrect, respectively.