EFFICIENT HANDLING OF REGISTER FILES

• US 20170046160A1
• Filed: 03/31/2016
• Published: 02/16/2017
• Est. Priority Date: 08/14/2015
• Status: Abandoned Application

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: SETH, Kiran Ravi, MADHAVAN, Raghaven, SMITH, Rodney Wayne, TEKMEN, Yusuf Cagatay
• Application Number:
  US15/086,055
• Publication Number:
  US 20170046160A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 9/30098 Register arrangements
• CPC Class Codes: G06F 9/384 Register renaming

Abstract

Systems and methods of handling a register file include, in a first instruction set architecture (ISA) mode assigning a first subset of tracking resources to logical registers of a first logical register subset for tracking mappings to full granularity and first lower granularity physical registers of a first physical register subset, and assigning a second subset of tracking resources to logical registers of a second logical register subset for tracking mappings to second lower granularity physical registers of the first physical register subset. The second subset of tracking resources are configured for tracking at least the logical registers of the second logical register subset mappings to physical registers of a second physical register subset in a second ISA mode, wherein the second physical register subset is available to the second ISA mode but not the first ISA mode.

Claims

1. A method of operating a processor, the method comprising:

in a first instruction set architecture (ISA) mode;

assigning a first subset of tracking resources to logical registers of a first logical register subset for tracking mappings to full granularity physical registers and first lower granularity physical registers of a first physical register subset; and

assigning a second subset of tracking resources to logical registers of a second logical register subset for tracking mappings to second lower granularity physical registers of the first physical register subset,

wherein the second subset of tracking resources are configured for tracking at least mappings of the logical registers of the second logical register subset to physical registers of a second physical register subset in a second ISA mode,

wherein the second physical register subset is available to the second ISA mode but not the first ISA mode.

2. The method of claim 1, wherein the first ISA mode is an A32 mode, the second ISA mode is an A64 mode.

3. The method of claim 2, wherein the full granularity physical registers are 64-bit registers, the first lower granularity physical registers are lower 32-bit halves of 64-bit registers, and the second lower granularity physical registers are upper 32-bit halves of 64-bit registers.

4. The method of claim 1, wherein the tracking resources comprise attributes which indicate granularity of access.

5. The method of claim 1, further comprising writing to a first lower granularity physical register or a second lower granularity physical register based on the first subset of tracking resources or the second subset of tracking resources, respectively.

6. The method of claim 5, comprising writing to the first lower granularity physical register or the second lower granularity physical register, without first reading data stored in the first lower granularity physical register or the second lower granularity physical register, respectively.

7. The method of claim 1, further comprising reading from a first lower granularity physical register or a second lower granularity physical register based on the first subset of tracking resources or the second subset of tracking resources, respectively.

8. The method of claim 7, further comprising shifting data read from the second lower granularity physical register to the first lower granularity physical register for a lower granularity read operation.

14. The apparatus of claim 1, further comprising read logic configured to read from a first lower granularity physical register or a second lower granularity physical register based on the first subset of tracking resources or the second subset of tracking resources, respectively.

15. The apparatus of claim 14, further comprising shift logic configured to shift data read from the second lower granularity physical register to the first lower granularity physical register for a lower granularity read operation.

22. The non-transitory computer-readable storage medium of claim 1, wherein the tracking resources comprise attributes which indicate granularity of access.

9. An apparatus comprising:

a processor configured to operate in a first instruction set architecture (ISA) mode or a second ISA mode, wherein the processor comprises a rename map table (RMT) configured to track logical register names to physical register names of physical registers of a physical register file (PRF), wherein the RMT comprises;

a first subset of tracking resources configured to track mappings of logical registers of a first logical register subset to full granularity physical registers and first lower granularity physical registers of a first physical register subset of the PRF in the first ISA mode; and

a second subset of tracking resources configured to track mappings of logical registers of a second logical register subset to second lower granularity physical registers of the first physical register subset of the PRF in the first ISA mode,

wherein the second subset of tracking resources are configured to track at least mappings of the logical registers of the second logical register subset to physical registers of a second physical register subset of the PRF in the second ISA mode,

wherein the second physical register subset is available to the second ISA mode but not the first ISA mode.

10. The apparatus of claim 9, wherein the first ISA mode is an A32 mode, the second ISA mode is an A64 mode.

11. The apparatus of claim 10, wherein the full granularity physical registers are 64-bit registers, the first lower granularity physical registers are lower 32-bit halves of 64-bit registers, and the second lower granularity physical registers are upper 32-bit halves of 64-bit registers.

12. The apparatus of claim 9, wherein the tracking resources comprise attributes which indicate granularity of access.

13. The apparatus of claim 9, wherein the processor comprises write logic configured to write to a first lower granularity physical register or a second lower granularity physical register based on the first subset of tracking resources or the second subset of tracking resources, respectively.

16. An apparatus comprising:

means for executing instructions in a first instruction set architecture (ISA) mode or a second ISA mode, wherein the means for executing comprises;

a first means for tracking assigned to logical registers of a first logical register subset, for tracking mappings to full granularity physical registers and first lower granularity physical registers of a first physical register subset in the first ISA mode; and

a second means for tracking assigned to logical registers of a second logical register subset, for tracking mappings to second lower granularity physical registers of the first physical register subset in the first ISA mode,

wherein the second means for tracking for tracking comprises means for tracking at least mappings of the logical registers of the second logical register subset to physical registers of a second physical register subset in the second ISA mode,

wherein the second physical register subset is available to the second ISA mode but not the first ISA mode.

17. The apparatus of claim 16, wherein the first ISA mode is an A32 mode, the second ISA mode is an A64 mode.

18. The apparatus of claim 17, wherein the full granularity physical registers are 64-bit registers, the first lower granularity physical registers are lower 32-bit halves of 64-bit registers, and the second lower granularity physical registers are upper 32-bit halves of 64-bit registers.

19. A non-transitory computer-readable storage medium comprising code, which, when executed by a processor, causes the processor to manage tracking resources for logical registers in first and second instruction set architecture (ISA) modes, the non-transitory computer-readable storage medium comprising:

code for assigning, in the first ISA mode, a first subset of tracking resources to logical registers of a first logical register subset for tracking mappings to full granularity physical registers and first lower granularity physical registers of a first physical register subset; and

code for assigning, in the first ISA mode, a second subset of tracking resources to logical registers of a second logical register subset for tracking mappings to second lower granularity physical registers of the first physical register subset,

wherein the second subset of tracking resources are configured for tracking at least mappings of the logical registers of the second logical register subset to physical registers of a second physical register subset in a second ISA mode,

wherein the second physical register subset is available to the second ISA mode but not the first ISA mode.

20. The non-transitory computer-readable storage medium of claim 19, wherein the first ISA mode is an A32 mode, the second ISA mode is an A64 mode.

21. The non-transitory computer-readable storage medium of claim 20, wherein the full granularity physical registers are 64-bit registers, the first lower granularity physical registers are lower 32-bit halves of 64-bit registers, and the second lower granularity physical registers are upper 32-bit halves of 64-bit registers.

23. The non-transitory computer-readable storage medium of claim 19, further comprising code for writing to a first lower granularity physical register or a second lower granularity physical register based on the first subset of tracking resources or the second subset of tracking resources, respectively.

24. The non-transitory computer-readable storage medium of claim 23, comprising code for writing to the first lower granularity physical register or the second lower granularity physical register, without first reading data stored in the first lower granularity physical register or the second lower granularity physical register, respectively.

25. The non-transitory computer-readable storage medium of claim 19, further comprising code for reading from a first lower granularity physical register or a second lower granularity physical register based on the first subset of tracking resources or the second subset of tracking resources, respectively.

26. The non-transitory computer-readable storage medium of claim 25, further comprising code for shifting data read from the second lower granularity physical register to the first lower granularity physical register for a lower granularity read operation.