CORE PRIORITIZATION FOR HETEROGENEOUS ON-CHIP NETWORKS

• US 20170046198A1
• Filed: 04/24/2014
• Published: 02/16/2017
• Est. Priority Date: 04/24/2014
• Status: Active Grant

• Current Assignee: Empire Technology Development LLC (Allied Inventors Management, LLC)
• Original Assignee: Empire Technology Development LLC (Allied Inventors Management, LLC)
• Inventors: Solihin, Yan
• Granted Patent: US 10,445,131 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 1/3243 Power saving in microcontroller unit
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G06F 2009/45583 Memory management, e.g. access or allocation
• CPC Class Codes: G06F 9/45558 Hypervisor-specific management and integration aspects
• CPC Class Codes: G06F 9/4818 Priority circuits therefor
• CPC Class Codes: G06F 9/505 considering the load
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A processor may comprise a plurality of cores operating at heterogeneous frequencies communicatively coupled by a network of routers also operating at heterogeneous frequencies. A core may be prioritized for thread execution based on operating frequencies of routers on a path from the core to a memory controller. Relatively higher priority may be assigned to cores having a path comprising only routers operating at a relatively higher frequency. A combined priority for thread execution may be based on core frequency, router frequency, and the frequency of routers on a path from the core to a memory controller. A core may be selected based primarily on core operating frequency when cache misses fall below a threshold value.

Claims

1. A system, comprising:

a processor comprising a plurality of cores, a plurality of routers, and one or more memory controllers communicatively coupled to the plurality of cores by the plurality of routers; and

a component configured at least to;

identify a first core of the plurality of cores, wherein the identification of the first core is based at least in part on a first determination that all routers in at least one path between the first core and at least one of the one or more memory controllers are operable at a first frequency;

identify a second core of the plurality of cores, wherein the identification of the second core is based at least in part on a second determination that all paths between the second core and a memory controller of the at least one memory controller comprise at least one router with a maximum operable frequency less than the first frequency;

assign a first thread to execute on the first core; and

assign a second thread to execute on the second core based at least in part on a determination that the first core is unavailable to execute the second thread.

2. The system of claim 1, wherein the component is further configured at least to:

cause an unassigned core of the plurality of cores to be selected to enter a sleep state, based at least in part on the second determination.

3. The system of claim 2, wherein the component is further configured at least to:

cause a router of the plurality of routers to enter a sleep state based at least in part on an additional determination that a maximum operable frequency of the router to be caused to enter the sleep state is less than the first frequency.

4. The system of claim 1, wherein the component is further configured at least to:

determine to assign an additional thread to execute on a core other than the first core, based at least in part on a maximum operable frequency of the first core.

5. The system of claim 1, wherein the component is further configured at least to:

determine to assign an additional thread to a core other than the first core, based at least in part on a cache miss rate of the additional thread being above a threshold value.

6. The system of claim 1, wherein the component is further configured at least to:

calculate a priority value for the first core based at least in part on an operable frequency of the first core, an operable frequency of a router nearest to the first core, and a minimum operable frequency of the routers on the at least one path to the at least one of the one or more memory controllers.

7. The system of claim 6, wherein the component is further configured at least to:

assign a first additional thread to execute on the first core, the assignment of the first additional thread being based at least in part on the priority value and an additional determination that a cache miss rate of the first additional thread is above a threshold; and

assign a second additional thread to execute on the second core, the assignment of the second additional thread being based at least in part on the additional determination that the cache miss rate of the first additional thread is below the threshold.

8. The system of claim 1, wherein the component includes an operating system or a hypervisor.

9. The system of claim 1, wherein the component is further configured at least to:

determine a priority of a memory controller based at least in part on the first determination; and

steer data to memory accessible to the memory controller, based on the priority of the memory controller.

10. A method, comprising:

identifying a first core of a plurality of cores of a processor, wherein the identification of the first core is based at least in part on a first determination that all routers in at least one path between the first core and at least one of the one or more memory controllers are operable at a first frequency; and

identifying a second core of the plurality of cores, wherein the identification of the second core is based at least in part on a second determination that ail paths between the second core and a memory controller of the at least one memory controller comprise at least one router with a maximum operable frequency less than the first frequency.

11. The method of claim 10, further comprising:

calculating a priority value for the first core, wherein the calculated priority value is based at least in part on the first determination.

12. The method of claim 11, wherein the calculated priority value is further based at least in part on a maximum operable frequency of the first core.

13. The method of claim 10, further comprising:

calculating a priority value for the first core based at least in part on an operable frequency of the first core, an operable frequency of a router nearest to the first core, and operable frequencies of routers on the at least one path from the first core to a memory controller of the one or more memory controllers.

14. The method of claim 10, further comprising:

selecting the second core to perform power gating, based at least in part on the second determination.

15. The method of claim 10, further comprising:

calculating a priority value for a memory controller of the at least one memory controller, the priority value based at least in part on operable frequencies of routers on a path from the first core to the memory controller.

16. The method of claim 10, further comprising:

determining a priority of a memory controller based at least in part on the first determination; and

steering data to memory accessible to the memory controller, based at least in part on the priority of the memory controller.

17. A computer readable storage medium that includes executable instructions stored thereon that, in response to execution by a computing device, cause the computing device to perform or cause to be performed at least:

identify a first core of a plurality of cores, wherein the identification of the first core is based at least in part on a first determination that all routers in at least one path between the first core and at least one memory controller are operable at a first frequency;

identify a second core of the plurality of cores, wherein the identification of the second core is based at least in part on a second determination that all paths between the second core and a memory controller of the at least one memory controller comprise at least one router with a maximum operable frequency less than the first frequency,

assign a first thread to execute on the first core; and

assign a second thread to execute on the second core based at least in part on a determination that the first core is unavailable to execute the second thread.

18. The computer readable storage medium of claim 17, further comprising instructions stored thereon that, in response to execution by the computing device, cause the computing device to perform or cause to be performed at least:

determine to assign an additional thread to execute on a core other than the first core, based at least in part on a maximum operable frequency of the first core.

19. The computer readable storage medium of claim 17, further comprising instructions stored thereon that, in response to execution by the computing device, cause the computing device to perform or cause to be performed at least:

evaluate information indicative of operable frequencies of routers on a path from the first core to the at memory controller.

20. The computer readable storage medium of claim 17, further comprising instructions stored thereon that in response to execution by the computing device, cause the computing device to perform or cause to be performed at least:

calculate a priority value for the first core based at least in part on an operable frequency of the first core, an operable frequency of a router nearest to the first core, and a minimum operable frequency of the routers on the at least one path to the at least one memory controller.

21. The computer readable storage medium of claim 20, further comprising instructions stored thereon that in response to execution by the computing device, cause the computing device to perform or cause to be performed at least:

assign an additional thread to execute on the first core, the assignment based at least in part on the priority value and an additional determination that a cache miss rate of the additional thread is above a threshold.

22. The computer readable storage medium of claim 17, further comprising instructions stored thereon that, in response to execution by die computing device, cause the computing device to perform or cause to be performed at least:

assign an additional thread to execute on the second core in response to a determination that a cache miss rate of the additional thread is below a threshold and a maximum operable frequency of the second core is greater than a maximum operable frequency of the first core.

23. The computer readable storage medium of claim 17, further comprising instructions stored thereon that, in response to execution by the computing device, cause the computing device to perform or cause to be performed at least:

associate memory for the first thread with a physical page frame served by a memory controller, wherein the memory controller is selected based at least in part on the first determination.