FLASH MEMORY CONTROLLER AND MEMORY DEVICE FOR ACCESSING FLASH MEMORY MODULE, AND ASSOCIATED METHOD

• US 20170046225A1
• Filed: 08/10/2016
• Published: 02/16/2017
• Est. Priority Date: 08/10/2015
• Status: Active Grant

• Current Assignee: Silicon Motion, Inc. (Silicon Motion)
• Original Assignee: Silicon Motion, Inc. (Silicon Motion)
• Inventors: Yang, Tsung-Chieh
• Granted Patent: US 10,089,174 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

A method for accessing a flash memory module includes: sequentially writing Nth-(N+K)th data to a plurality of flash memory chips of the flash memory module, and encoding the Nth-(N+K)th data to generate Nth-(N+K)th ECCs, respectively, where the Nth-(N+K) th ECCs are used to correct errors of the Nth-(N+K)th data, respectively, and N and K are positive integers; and writing the (N+K+1)th data to the plurality of flash memory chips of the flash memory module, and encoding the (N+K+1)th data with at least one of the Nth-(N+K)th ECCs to generate the (N+K+1)th ECC.

Claims

1. A method for accessing a flash memory module, comprising:

sequentially writing Nth-(N+K)th data to a plurality of flash memory chips of the flash memory module, and encoding the Nth-(N+K)th data to generate Nth-(N+K)th error correction codes (ECCs), respectively, where the Nth-(N+K)th ECCs are used to correct errors of the Nth-(N+K)th data, respectively, and N and K are positive integers; and

writing (N+K+1)th data to the plurality of flash memory chips of the flash memory module, and encoding the (N+K+1)th data with at least one of the Nth-(N+K)th ECCs, to generate (N+K+1)th ECC.

2. The method of claim 1, wherein K is 1, and the step of generating the (N+K+1)th ECC comprises:

encoding the (N+K)th ECC together with the (N+K+1)th data to generate the (N+K+1)th ECC.

3. The method of claim 1, wherein K is 1, and the step of generating the (N+K+1)th ECC comprises:

encoding the Nth ECC together with the (N+K+1)th data to generate the (N+K+1)th ECC.

4. The method of claim 1, wherein Nth-(N+K+1)th data is written to floating gates transistors of different word line groups of each flash memory chip of the plurality of flash memory chips, wherein each of the word line groups comprises a plurality of word lines.

5. The method of claim 1, wherein K is an integer within 1-M, and the Nth data is written to a first page of a super block of the plurality of flash memory chips, wherein the super block comprises a block of each flash memory chip of the plurality of flash memory chips;

and the (N+M+1)th data is written to a last page of the super block of the plurality of flash memory chips.

6. The method of claim 5, wherein the step of generating the (N+K+1) th ECC comprises

encoding the (N+K)th ECC together with the (N+K+1)th data to generate the (N+K+1)th ECC.

7. The method of claim 5, wherein the step of generating the (N+K+1) th ECC comprises:

encoding the (N+K-1)th ECC together with the (N+K+1)th data to generate the (N+K+1)th ECC.

8. The method of claim 5, further comprising:

writing the Nth-(N+K+1)th ECCs to at least one specific block of the flash memory module.

9. The method of claim 8, wherein the specific block is a single-level cell (SLC) block.

10. The method of claim 8, wherein K is an integer within 1-M, and the Nth data is written to a first page of a super block of the plurality of flash memory chips, wherein the super block comprise a block of each flash memory chip of the plurality of flash memory chips;

and the (N+M+1)th data is written to a last page of the super block of the plurality of flash memory chips.

11. The method of claim 10, further comprising:

writing the (N+K+1)th ECC stored in the specific block to another block, or writing the (N+K)th and (N+K+1)th ECCs to the other block.

12. The method of claim 11, wherein the specific block is a single-level cell (SLC) block, and the other block is a multiple-level cell (MLC) block, a triple-level cell (TLC) block, or a quad-level cell (QLC) block.

13. The method of claim 11, further comprising:

after the (N+K+1)th ECC is written to the other block, or the (N+K)th and (N+K+1)th ECCs are written to the other block, erasing the specific block.

14. The method of claim 11, further comprising:

reading specific data in the super block;

when an error that is uncorrectable by an ECC of the super block occurs when reading the specific data, reading the (N+K+1)th ECC stored in the other block, or reading the (N+K)th and the (N+K+1)th ECC stored in the other block, to perform error correction upon the specific data.

15. The method of claim 14, wherein the specific data is data in any page of the super block.

16. The method of claim 11, further comprising:

writing the Nth-(N+K+1)th ECCs to at least one specific block of the flash memory module, wherein the specific block is a single-level cell (SLC) block.

17. A flash memory controller, arranged to access a flash memory module, and comprising:

a memory, arranged to store a program code;

a microprocessor, arranged to execute the program code, to control access of the flash memory module; and

an encoder;

wherein the microprocessor sequentially writes the Nth-(N+K)th data to a plurality of flash memory chips in the flash memory module, respectively, and the encoder encodes the Nth-(N+K)th data to generate Nth-(N+K)th ECCs, respectively, the Nth-(N+K)th ECCs are arranged to perform error correction upon the Nth-(N+K)th data written to the plurality of flash memory chips, and N and K are positive integers; and

the microprocessor writes (N+K+1)th data to the plurality of flash memory chips of the flash memory module, and the encoder encodes at least one of the Nth-(N+K)th ECCs together with the (N+K+1)th data, to generate (N+K+1)th ECC.

18. The flash memory controller of claim 17, wherein K is 1, and the encoder encodes the (N+K)th ECC together with the (N+K+1)th data to generate the (N+K+1)th ECC.

19. The flash memory controller of claim 17, wherein K is 1, and the encoder encodes the Nth ECC together with the (N+K+1)th data to generate (N+K+1)th ECC.

20. The flash memory controller of claim 17, wherein the Nth-(N+K+1)th data is written to floating gate transistors of different word line groups of each flash memory chip of the plurality of flash memory chips, wherein each of the word line groups comprises a plurality of word lines.

21. The flash memory controller of claim 17, wherein K is an integer within 1-M, and the Nth data is written to a first page of a super block of the plurality of flash memory chips, wherein the super block comprises a block of each flash memory chip within the plurality of flash memory chips;

and the (N+M+1)th data is written to a last page of the super block of the plurality of flash memory chips.

22. The flash memory controller of claim 21, wherein the encoder encodes the (N+K)th ECC together with the (N+K+1)th data to generate the (N+K+1)th ECC.

23. The flash memory controller of claim 21, wherein the encoder encodes the (N+K-1)th ECC together with the (N+K+1)th data to generate the (N+K+1)th ECC.

24. The flash memory controller of claim 21, wherein the microprocessor writes the Nth-(N+K+1)th ECCs to at least one specific block of the flash memory module.

25. The flash memory controller of claim 24, wherein the specific block is an SLC block.

26. The flash memory controller of claim 24, wherein K is an integer within 1-M, and the Nth data is written to a first page of a super block of the plurality of flash memory chips, wherein the super block comprises a block of each flash memory chip within the plurality of flash memory chips;

and the (N+M+1)th data is written to a last page of the super block of the plurality of flash memory chips.

27. The flash memory controller of claim 26, wherein the microprocessor writes the (N+K+1)th ECC stored in the specific block to another block, or writes the (N+K)th and (N+K+1)th ECCs stored in the specific block to the other block.

28. The flash memory controller of claim 27, wherein the specific block is a single-level cell (SLC) block, and the other block is a multiple-level cell (MLC) block, a triple-level cell (TLC) block, or a quad-level cell (QLC) block.

29. The flash memory controller of claim 27, wherein the microprocessor erases the specific block after writing the (N+K+1)th ECC to the other block, or after writing the (N+K)th and (N+K+1)th ECCs to the other block.

30. The flash memory controller of claim 27, wherein the microprocessor reads a specific data in the super block;

and when an error that is uncorrectable by an ECC of the super block occurs when reading the specific data, the microprocessor reads the (N+K+1)th ECC stored within the other block, or reads the (N+K)th and (N+K+1)th ECC stored within the other block, to perform error correction upon the specific data.

31. The flash memory controller of claim 30, wherein the specific data is data in any page of the super block.

32. The flash memory controller of claim 27, wherein the microprocessor writes the Nth-(N+K+1)th ECCs to at least one specific block of the flash memory module, and the at least one specific block is an SLC block.

33. A memory apparatus, comprising:

a flash memory module; and

a flash memory controller, arranged to access the flash memory module;

wherein the flash memory controller sequentially writes Nth -(N+K)th data to a plurality of flash memory chips in the flash memory module, respectively, and encodes the Nth-(N+K)th data to generate Nth-(N+K)th ECCs, respectively;

the Nth-(N+K)th ECCs are arranged to perform error correction upon the Nth-(N+K)th data written to the plurality of flash memory chips, and N and K are positive integers; and

the flash memory controller writes (N+K+1)th data to the plurality of flash memory chips in the flash memory module, and encodes at least one of the Nth -(N+K)th ECCs together with the (N+K+1)th data, to generate (N+K+1)th ECC.

34. The memory apparatus of claim 33, wherein the flash memory controller writes the Nth-(N+K+1)th data to a plurality of blocks of the plurality of flash memory chips, and the plurality of blocks are multiple-level cell (MLC) blocks, triple-level cell (TLC) blocks, or quad-level cell (QLC) blocks;

and the flash memory controller writes the Nth-(N+K+1)th ECCs to at least one specific block of the flash memory module, wherein the specific block is an SLC block.