VARIABLE-SIZE FLASH TRANSLATION LAYER

• US 20170046273A1
• Filed: 10/31/2016
• Published: 02/16/2017
• Est. Priority Date: 01/22/2013
• Status: Active Grant

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Cohen, Earl T.
• Granted Patent: US 10,346,312 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 12/02 Addressing or allocation; Relocation program address sequencing G06F9/00; arrangements for selecting an address in a digital store G11C8/00
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0292 using tables or multilevel address translation means G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10
• CPC Class Codes: G06F 12/04 Addressing variable-length words or parts of words
• CPC Class Codes: G06F 12/10 Address translation
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/401 Compressed data
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0661 Format or protocol conversion arrangements
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 29/04 Detection or location of defective memory elements , e.g. cell constructio details, timing of test signals
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method for using a variable-size flash translation layer. The method includes reading an entry in a map based on a read logical block address in a read request to obtain both a physical address of a particular page in a memory and information regarding compressed data with a variable size; converting the information to both an address in the particular page and a number of read units in the memory that contain the compressed data; and reading the compressed data from at least the particular page in the memory based on the address and the number of read units.

Claims

1. A method for using a variable-size flash translation layer, comprising the steps of:

reading an entry in a map based on a read logical block address in a read request to obtain both a physical address of a particular page in a memory and information regarding compressed data with a variable size;

converting the information to both an address in the particular page and a number of read units in the memory that contain the compressed data; and

reading the compressed data from at least the particular page in the memory based on the address and the number of read units.

2. The method according to claim 1, further comprising the steps of:

performing error correction decoding on each of the read units as read from the memory to generate corrected data; and

extracting the compressed data from the corrected data.

3. The method according to claim 2, further comprising the steps of:

decompressing the compressed data to generate read data; and

transferring the read data to a host.

4. The method according to claim 1, further comprising the steps of:

determining that at least a portion of the compressed data is in one or more subsequent read units in a subsequent page of the memory; and

reading only the one or more subsequent read units from the subsequent page.

5. The method according to claim 1, further comprising the steps of:

receiving a write request to store write data in the memory;

compressing the write data to generate the compressed data;

writing in the particular page at least a portion of the compressed data; and

storing in the map the physical address of the particular page, an offset in the particular page to the compressed data, and a length of the compressed data.

6. The method according to claim 1, further comprising the steps of:

receiving a write request to store write data in the memory; and

writing in the particular page a header that includes at least a portion of a write logical block address of the write request.

7. The method according to claim 1, wherein

at least one of the number of read units includes at least some different data corresponding to another logical block address different than the read logical block address.

8. The method according to claim 1, wherein

at least one of the number of the read units includes one or more headers and at least a portion of the compressed data.

9. The method according to claim 1, wherein the steps are performed in a solid-state drive.

10. An apparatus comprising:

a memory configured to store data; and

a controller configured to

process a plurality of input/output requests to read/write to/from the memory,

read an entry in a map based on a read logical block address in a read request to obtain both a physical address of a particular page in the memory and information regarding compressed data with a variable size,

convert the information to both an address in the particular page and a number of read units in the memory that contain the compressed data, and

read the compressed data from at least the particular page in the memory based on the address and the number of read units.

11. The apparatus according to claim 10, wherein the controller is further configured to

perform error correction decoding on each of the read units as read from the memory to generate corrected data, and

extract the compressed data from the corrected data.

12. The apparatus according to claim 11, wherein the controller is further configured to

decompress the compressed data to generate read data, and

transfer the read data to a host.

13. The apparatus according to claim 10, wherein the controller is further configured to

determine that at least a portion of the compressed data is in one or more subsequent read units in a subsequent page of the memory, and

read only the one or more subsequent read units from the subsequent page.

14. The apparatus according to claim 10, wherein the controller is further configured to

receive a write request to store write data in the memory,

compress the write data to generate the compressed data,

write in the particular page at least a portion of the compressed data, and

store in the map the physical address of the particular page, an offset in the particular page to the compressed data, and a length of the compressed data.

15. The apparatus according to claim 10, wherein the controller is further configured to

receive a write request to store write data in the memory, and

write in the particular page a header that includes at least a portion of a write logical block address of the write request.

16. The apparatus according to claim 10, wherein

at least one of the number of read units includes at least some different data corresponding to another logical block address different than the read logical block address.

17. The apparatus according to claim 10, wherein

at least one of the number of the read units includes one or more headers and at least a portion of the compressed data.

18. The apparatus according to claim 10, wherein the memory and the controller are part of a solid-state drive.

19. An apparatus comprising:

an interface configured to process a plurality of read/write operations to/from a memory; and

a control circuit configured to

read an entry in a map based on a read logical block address in a read request to obtain both a physical address of a particular page in the memory and information regarding compressed data with a variable size,

convert the information to both an address in the particular page and a number of read units in the memory that contain the compressed data, and

read the compressed data from at least the particular page in the memory based on the address and the number of read units.

20. The apparatus according to claim 19, wherein the interface and the control circuit are part of a solid-state drive.