PIXEL CIRCUIT, DISPLAY DEVICE AND DRIVE METHOD THEREOF

• US 20170047007A1
• Filed: 08/10/2015
• Published: 02/16/2017
• Est. Priority Date: 04/03/2015
• Status: Abandoned Application

• Current Assignee: BOE Technology Group Co., Ltd.
• Original Assignee: BOE Technology Group Co., Ltd.
• Inventors: YIN, Jingwen, WANG, Lirong
• Application Number:
  US15/021,332
• Publication Number:
  US 20170047007A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G09G 2300/0809 Several active elements per pixel in active matrix panels
• CPC Class Codes: G09G 2300/0819 used for counteracting undesired variations, e.g. feedback or autozeroing
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2300/0852 being a dynamic memory with more than one capacitor
• CPC Class Codes: G09G 2310/0245 Clearing or presetting the whole screen independently of waveforms, e.g. on power-on G09G2310/063 takes precedence
• CPC Class Codes: G09G 2310/061 for resetting or blanking
• CPC Class Codes: G09G 2320/0233 Improving the luminance or brightness uniformity across the screen
• CPC Class Codes: G09G 2320/0646 Modulation of illumination source brightness and image signal correlated to each other
• CPC Class Codes: G09G 3/32 semiconductive, e.g. using light-emitting diodes [LED]
• CPC Class Codes: G09G 3/3233 with pixel circuitry controlling the current through the light-emitting element
• CPC Class Codes: G09G 3/325 the data current flowing through the driving transistor during a setting phase, e.g. by using a switch for connecting the driving transistor to the data driver
• CPC Class Codes: G09G 3/3258 with pixel circuitry controlling the voltage across the light-emitting element
• CPC Class Codes: G09G 3/3266 Details of drivers for scan electrodes
• CPC Class Codes: G09G 3/3291 in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements

Abstract

The present disclosure provides a pixel circuit comprising a light-emitting element, a drive transistor comprising a first electrode for receiving a first level signal and a second electrode for providing a drive current to the light-emitting element, and a storage module for storing data inputted in a data write phase and providing the data to a gate of the drive transistor in a light-emitting phase, wherein a first terminal of the storage module is connected with the gate of the drive transistor, and a second terminal of the storage module is connected with a second electrode of the drive transistor. The storage module is further configured to store a threshold voltage of the drive transistor. The present disclosure further provides a display device and a drive method. When the display device performs display, brightness of the light-emitting element does not vary with a threshold drift of the drive transistor.

Claims

1. A pixel circuit comprising:

a light-emitting element;

a drive transistor comprising a first electrode for receiving a first level signal and a second electrode for providing a drive current to the light-emitting element; and

a storage module for storing data inputted in a data write phase and providing the data to a gate of the drive transistor in a light-emitting phase,

wherein a first terminal of the storage module is connected with the gate of the drive transistor, and a second terminal of the storage module is connected with a second electrode of the drive transistor, and

wherein the storage module is further configured to store a threshold voltage of the drive transistor.

2. The pixel circuit according to claim 1, wherein the storage module is configured to connect the gate of the drive transistor with the second electrode when the first level signal is at a low level.

3. The pixel circuit according to claim 2, wherein the first level signal is at a low level prior to the data write phase and at a high level in the data write phase and the light-emitting phase.

4. The pixel circuit according to claim 1, further comprising a data write module configured to input a data signal to the storage module in the data write phase.

5. The pixel circuit according to claim 4, wherein the data write module comprises a data write transistor, wherein a gate of the data write transistor is connected with a first gate line, and wherein a first electrode of the data write transistor is configured to receive a signal from a data line in the data write phase, and a second electrode of the data write transistor that is connected with a third terminal of the storage module.

6. The pixel circuit according to claim 4, wherein the first electrode of the data write transistor is configured to be connected with a reference voltage line in a reset phase prior to start of the data write phase.

7. The pixel circuit according to claim 5, wherein the storage module comprises:

a first storage capacitor disposed between the third terminal and first terminal of the storage module,

a second storage capacitor disposed between the third terminal of the storage module and a ground level, and

a control transistor configured to control a circuit connection between the first terminal and third terminal of the storage module, a gate of the control transistor connected with a second gate line.

8. A display device comprising a power supply and N×

M pixel cells divided and arranged in N rows×

M columns, where N and M are integers greater than 1, each of said pixel cells being provided therein with a pixel circuit according to claim 1,

wherein the power supply is used to provide a first level signal to the pixel circuit and the power supply is configured to provide a low-level signal prior to a data write phase and provide a high-level signal in the data write phase and a light-emitting phase.

9. The display device according to claim 8, wherein the display device comprises N sets of gate lines and M data lines, the N sets of gate lines correspond one-to-one with N rows of said pixel cells, and the M data lines correspond one-to-one with M columns of said pixel cells, and

wherein each set of gate lines comprises a first gate line for providing a control signal to a gate of a data write transistor of the data write module to provide data from the data line to the storage module.

10. The display device according to claim 9, further comprising a reference voltage line for providing a reference voltage to a first electrode of the data write transistor in a reset phase prior to the data write phase.

11. The display device according to claim 10, wherein the reference voltage line is formed integrally with the data line.

12. The display device according to claim 9, wherein each set of said gate lines further comprises a second gate line configured to control a control transistor connected between the first terminal and second terminal of the storage module.

13. A drive method for driving the display device according to claim 8, the drive method comprising a plurality of display cycles, each of said display cycles including a reset and threshold voltage collecting phase, a data write phase and a light-emitting phase, the drive method comprising:

in the reset and threshold voltage collecting phase, providing a low level from the power supply to the drive transistor so that the storage module stores the threshold voltage of the drive transistor; and

providing a high level from the power supply to the drive transistor in the data write phase and the light-emitting phase.

14. The drive method according to claim 13, wherein the display device comprises N sets of gate lines and M data lines, wherein the N sets of gate lines correspond one-to-one with N rows of said pixel cells, and the M data lines correspond one-to-one with M columns of said pixel cells, where N and M are integers greater than 1, each set of gate line comprising a first gate line for providing a control signal to a data write transistor of a data write module to provide data from the data line to the storage module, the drive method comprising:

in the data write phase, providing a level enabling the data write transistor to turn on to a gate of the data write transistor via the first gate line, and providing a data voltage to a first electrode of the data write transistor via the data line; and

in the light-emitting phase, providing a level enabling the data write transistor to turn off to the gate of the data write transistor via the first gate line.

15. The drive method according to claim 14, further comprising in the reset and threshold voltage collecting phase:

providing a level enabling the data write transistor to turn on to the gate of the data write transistor via the first gate line, and providing a reference voltage to the first electrode of the data write transistor via the data line.

16. The drive method according to claim 14, wherein each set of said gate lines further comprises a second gate line configured to control a control transistor disposed between the first terminal and second terminal of the storage module, the drive method comprising:

in the reset and threshold voltage collecting phase, providing a level enabling the control transistor to turn on to the second gate line;

in the data write phase, providing a level enabling the control transistor to turn off to the second gate line; and

in the light-emitting phase, providing a level enabling the control transistor to turn off to the second gate line.

17. The pixel circuit according to claim 6, wherein the storage module comprises:

a first storage capacitor disposed between the third terminal and first terminal of the storage module,

a second storage capacitor disposed between the third terminal of the storage module and a ground level, and

a control transistor configured to control a circuit connection between the first terminal and third terminal of the storage module, wherein a gate of the control transistor is connected with a second gate line.

18. The display device according to claim 10, wherein each set of said gate lines further comprises a second gate line configured to control a control transistor connected between the first terminal and second terminal of the storage module.

19. The display device according to claim 11, wherein each set of said gate lines further comprises a second gate line configured to control a control transistor connected between the first terminal and second terminal of the storage module.