METHODS FOR MANUFACTURING A SEMICONDUCTOR DEVICE

• US 20170047257A1
• Filed: 08/12/2016
• Published: 02/16/2017
• Est. Priority Date: 08/12/2015
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: YOON, JUNHO, CHANG, KISOO, HAN, KYOUNGHOON
• Granted Patent: US 9,859,163 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/76814 post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823425 manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method for manufacturing a semiconductor device includes forming gate structures spaced apart from each other on a substrate, gate spacers covering sidewalls of the gate structures, and an interlayer insulating layer covering the gate spacers, forming a contact hole that penetrates the interlayer insulating layer to expose a sidewall of at least one of the gate spacers, forming a sacrificial gap-fill pattern filling a lower portion of the contact hole, forming a contact spacer on a sidewall of the contact hole having the sacrificial gap-fill pattern, and forming a contact filling the contact hole after removing the sacrificial gap-fill pattern.

Claims

1. A method for manufacturing a semiconductor device, the method comprising:

forming a plurality of gate structures, a plurality of gate spacers, and an interlayer insulating layer on a substrate, the plurality of gate structures spaced apart from each other in a first direction, the plurality of gate spacers spaced apart from each other in said first direction and covering sidewalls of each of the plurality of gate structures, and the interlayer insulating layer covering each of the plurality of gate spacers;

forming a contact hole that penetrates the interlayer insulating layer to expose a sidewall of at least one of the plurality of gate spacers;

forming a sacrificial gap-fill pattern filling a lower portion of the contact hole;

forming a contact spacer on a sidewall of the contact hole having the sacrificial gap-fill pattern; and

forming a contact filling the contact hole after removing the sacrificial gap-fill pattern.

2. The method of claim 1, wherein the forming of the contact hole comprises:

forming a mask pattern on the interlayer insulating layer; and

patterning the interlayer insulating layer using the mask pattern.

3. The method of claim 2, wherein the mask pattern is a carbon-based spin-on-hardmask (SOH) pattern, a silicon-based SOH pattern, an amorphous carbon pattern, or a photoresist pattern.

4. The method of claim 2, wherein the mask pattern includes the same material as the sacrificial gap-fill pattern.

5. The method of claim 1, wherein at least a portion of the gate spacer is removed when the contact hole is formed, and

wherein the contact spacer is substituted for the removed portion of the gate spacer.

6. The method of claim 1, wherein a bottom surface of the contact spacer is disposed at the same level as a bottom of the recess region.

7. The method of claim 1, wherein a bottom surface of the contact spacer is disposed at the same level as a top surface of the sacrificial gap-fill pattern.

8. The method of claim 1, wherein the sacrificial gap-fill pattern is a carbon-based spin-on-hardmask (SOH) pattern, a silicon-based SOH pattern, or an amorphous carbon pattern.

9. The method of claim 1, wherein the forming of the sacrificial gap-fill pattern comprises:

forming a sacrificial gap-fill layer filling the contact hole on the substrate; and

performing an etch-back process on the sacrificial gap-fill layer.

10. The method of claim 1, wherein the contact spacer includes the same insulating material as the gate spacer.

11. The method of claim 1, wherein the contact spacer and the gate spacer include insulating materials different from each other.

12. The method of claim 1, wherein the contact spacer includes at least one of silicon oxynitride, silicon oxide, silicon-carbon nitride, silicon-boron nitride, silicon-carbon oxynitride, or silicon nitride.

13. The method of claim 1, wherein the contact comprises:

a first portion being in contact with the contact spacer; and

a second portion being in contact with the gate spacer, and

wherein a width of the first portion of the contact is equal to or greater than a width of the second portion of the contact.

14. The method of claim 1 further comprising:

forming a source/drain region between two gate structures of the plurality of gate structures on the substrate, the interlayer insulating layer covering the plurality of gate spacers and the source/drain region; and

forming a contact hole that penetrates the interlayer insulating layer to expose a top surface of the source/drain region and sidewalls of the plurality of gate spacers.

15. A method, comprising:

providing a substrate;

providing a gate structure on the substrate;

providing a gate spacer disposed on a sidewall of the gate structure and having a recess region formed in an upper sidewall of the gate spacer;

providing a contact spacer filling the recess region and contacting a sidewall of the gate spacer of the recess region; and

providing an electrical contact being in contact with the sidewall of the gate spacer and a sidewall of the contact spacer.

16. The method of claim 15, wherein a distance from the gate structure to the sidewall of the gate spacer being in contact with the contact spacer is smaller than a distance from the gate structure to a sidewall of the gate spacer being in contact with the contact.

17. The method of claim 15, wherein providing the electrical contact includes:

forming a contact hole that penetrates an interlayer insulating layer disposed on the substrate to expose a sidewall of the gate spacer;

forming a sacrificial gap-fill pattern at a lower portion of the contact hole;

forming the contact spacer on a sidewall of the contact hole having the sacrificial gap-fill pattern; and

forming an electrical contact after removing the sacrificial gap-fill pattern.

18. The method of claim 15, wherein an outer sidewall of the gate spacer at the recess region contacts a first sidewall of the contact spacer at the recess region.

19. The method of claim 15, wherein a top surface of the of the gate spacer at the recess region contacts a bottom surface of the contact spacer at the recess region.

20. The method of claim 15, wherein the electrical contact comprises:

a first portion being in contact with the contact spacer; and

a second portion being in contact with the gate spacer, and

wherein a width of the first portion of the electrical contact is equal to or greater than a width of the second portion of the electrical contact.