PACKAGING OPTOELECTRONIC COMPONENTS AND CMOS CIRCUITRY USING SILICON-ON-INSULATOR SUBSTRATES FOR PHOTONICS APPLICATIONS

• US 20170047312A1
• Filed: 08/13/2015
• Published: 02/16/2017
• Est. Priority Date: 08/13/2015
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Budd, Russell A., Meghelli, Mounir, Orcutt, Jason Scott, Plouchart, Jean-Olivier
• Granted Patent: US 9,786,641 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G02B 2006/12061 Silicon
• CPC Class Codes: G02B 2006/12069 Organic material
• CPC Class Codes: G02B 2006/12123 Diode
• CPC Class Codes: G02B 2006/12147 Coupler
• CPC Class Codes: G02B 6/122 Basic optical elements, e.g. light-guiding paths
• CPC Class Codes: G02B 6/1221 made from organic materials
• CPC Class Codes: G02B 6/124 Geodesic lenses or integrated gratings
• CPC Class Codes: G02B 6/132 by deposition of thin films
• CPC Class Codes: G02B 6/34 utilising prism or grating G02B6/293 takes precedence
• CPC Class Codes: G02B 6/4204 the coupling comprising intermediate optical elements, e.g. lenses, holograms encapsulated active devices H01S5/02208, H01L33/52
• CPC Class Codes: G02B 6/4214 the intermediate optical element having redirecting reflective means, e.g. mirrors, prisms for deflecting the radiation from horizontal to down- or upward direction toward a device G02B6/4246 takes precedence
• CPC Class Codes: G02B 6/4274 Electrical aspects G02B6/4263 and G02B6/4265 take precedence
• CPC Class Codes: G02B 6/428 containing printed circuit boards [PCB]
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 2223/58 Structural electrical arrangements for semiconductor devices not otherwise provided for
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/367 Cooling facilitated by shape of device H01L23/38, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence
• CPC Class Codes: H01L 23/3675 characterised by the shape of the housing
• CPC Class Codes: H01L 23/485 : consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49838 : Geometry or layout
• CPC Class Codes: H01L 23/49894 : Materials of the insulating layers or coatings
• CPC Class Codes: H01L 23/585 : comprising conductive layers or plates or strips or rods or rings H01L23/60, H01L23/62, H01L23/64, H01L23/66 take precedence
• CPC Class Codes: H01L 25/117 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/167 : comprising optoelectronic devices, e.g. LED, photodiodes
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/1203 : the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01S 5/021 : Silicon based substrates
• CPC Class Codes: H01S 5/0215 : Bonding to the substrate
• CPC Class Codes: H01S 5/02325 : Mechanically integrated components on mount members or optical micro-benches
• CPC Class Codes: H01S 5/0237 : by soldering
• CPC Class Codes: H01S 5/02469 : Passive cooling, e.g. where heat is removed by the housing as a whole or by a heat pipe without any active cooling element like a TEC
• CPC Class Codes: H01S 5/026 : Monolithically integrated components, e.g. waveguides, monitoring photo-detectors, drivers stabilisation of output H01S5/06
• CPC Class Codes: H01S 5/1032 : Coupling to elements comprising an optical axis that is not aligned with the optical axis of the active region
• CPC Class Codes: H01S 5/11 : Comprising a photonic bandgap structure
• CPC Class Codes: H01S 5/18341 : Intra-cavity contacts
• CPC Class Codes: H01S 5/18361 : Structure of the reflectors, e.g. hybrid mirrors
• CPC Class Codes: H01S 5/1838 : Reflector bonded by wafer fusion or by an intermediate compound

Abstract

Package structures and methods are provided to integrate optoelectronic and CMOS devices using SOI semiconductor substrates for photonics applications. For example, a package structure includes an integrated circuit (IC) chip, and an optoelectronics device and interposer mounted to the IC chip. The IC chip includes a SOI substrate having a buried oxide layer, an active silicon layer disposed adjacent to the buried oxide layer, and a BEOL structure formed over the active silicon layer. An optical waveguide structure is patterned from the active silicon layer of the IC chip. The optoelectronics device is mounted on the buried oxide layer in alignment with a portion of the optical waveguide structure to enable direct or adiabatic coupling between the optoelectronics device and the optical waveguide structure. The interposer is bonded to the BEOL structure, and includes at least one substrate having conductive vias and wiring to provide electrical connections to the BEOL structure.

Claims

1. A package structure comprising:

a photonics package comprising;

an integrated circuit chip comprising a silicon-on-insulator (SOI) substrate, wherein the SOI substrate comprises a buried oxide layer, an active silicon layer disposed adjacent to the buried oxide layer, and a BEOL (back-end-of-line) structure formed over the active silicon layer;

an integrated optical waveguide structure patterned from the active silicon layer of the integrated circuit chip;

an optoelectronics device mounted on the buried oxide layer of the integrated circuit chip in alignment with at least a portion of the integrated optical waveguide structure; and

an interposer bonded to the REM, structure of the integrated circuit chip, the interposer comprising at least one substrate having a plurality of conductive through vias and. wiring to provide electrical connections to the BEOL structure.

2. The package structure of claim 1, wherein the integrated optical waveguide structure is adiabatically coupled to the optoelectronics device through the buried oxide layer.

3. The package structure of claim 1, wherein the integrated optical waveguide structure comprises a vertical grating coupler to couple light between the optical waveguide structure and the optoelectronics device.

4. The package structure of claim 1, wherein the optoelectronics device comprises at least one of a laser diode, a photodiode, a photonics device, or a combination thereof.

5. The package structure of claim 1, further comprising one or more conductive vias formed through the buried oxide layer and into the BEOL structure to provide electrical connections between the optoelectronics device and active circuitry of the integrated circuit chip.

6. The package structure of claim 1, wherein the at least one substrate of the interposer is formed of glass or high-resistivity silicon or other insulator material.

7. The package structure of claim 1, further comprising a capping layer formed on the buried oxide layer to prevent light from leaking out of the integrated optical waveguide structure through the buried oxide layer.

8. The package structure of claim 1, wherein the integrated circuit chip comprises at least one of optical receiver circuitry and optical transmitter circuitry formed as part of the active silicon layer.

9. The package structure of claim 1, further comprising a flexible polymer waveguide haying a waveguide core bonded directly to a portion of the buried oxide layer in alignment with an end portion of the integrated optical waveguide structure, wherein the waveguide core is adiabatically coupled to the end portion of the integrated optical waveguide structure through the buried oxide layer.

10. The package structure of claim 1, further comprising an application board, wherein the photonics package is flip-chip mounted to the application board by bonding the interposer of the photonics package to a first side of the application board.

11. The package structure of claim 10, further comprising a second integrated circuit chip mounted to the first side of the application board, wherein the application board comprises a plurality of high-speed transmission lines formed on the first side of the application board to provide electrical communication between the photonics package and the second integrated circuit chip.

12. The package structure of claim 1, further comprising:

a second integrated circuit chip;

a package interposer, wherein the photonics package is mounted to a first side of the package interposer and wherein the second integrated circuit chip is mounted to a second side of the package interposer, opposite the first side of the package interposer, wherein the package interposer comprises electrical wiring and through vias to provide electrical connections between the photonics package and the second integrated circuit chip; and

an application board having an integrated recess formed in one side of the application hoard, wherein the package interposer is mounted to the application board with at least a portion of the photonics package disposed within the integrated recess of the application board;

wherein the application board comprises a plurality of thermal vim formed therein in alignment with the integrated recess, wherein photonics package is disposed within the integrated recess such that a backside of the optoelectronics device of the photonics package is in thermal contact with the plurality of thermal vias.

13. The package structure of claim 12, wherein the integrated circuit chip of the photonics package comprises at least one of optical receiver circuitry and optical transmitter circuitry formed as part of the active silicon layer, wherein the optoelectronics device comprises at least one of a laser diode and a photodiode, and wherein the second integrated circuit chip comprises a microprocessor.

14. The package structure of claim 12, wherein the application board comprises a hole formed through the application board, wherein the package structure further comprises a optical fiber device with an integrated lens aligned to one end of the hole, and wherein the integrated optical waveguide structure of the photonics package comprises a vertical grating coupler that is disposed in alignment with another end of the hole, wherein light is transmitted through the hole in the application board between the integrated lens and the vertical grating coupler.

15. The package structure of claim 1, further comprising:

a second integrated circuit chip;

a package interposer having a hole formed through the package interposer; and

an application board;

wherein the second integrated circuit chip is flip-chip mounted to a first side of the package interposer;

wherein the photonics package is mounted to a front side of the second integrated circuit chip and disposed within the hole of the package interposer;

wherein a second side of the package interposer is mounted to a first side of the application hoard;

wherein the application board comprises a heat sink formed on the first side of the application board, and a plurality of thermal vias formed therein in alignment with heat sink;

wherein photonics package is disposed within the hole of the package interposer such that a backside of the optoelectronics device of the photonics package is in thermal contact with the heat sink formed on the first side of the application board.

16. The package structure of claim 15, wherein the integrated circuit chip of the photonics package comprises at least one of optical receiver circuitry and optical transmitter circuitry formed as part of the active silicon layer, wherein the optoelectronics device comprises at least one of a laser diode, a photodiode, a photonics device, and a combination thereof, and wherein the second integrated circuit chip comprises a microprocessor.

17. The package structure of claim 15, wherein the application board comprises a hole formed through the application board, wherein the package structure further comprises a optical fiber device with an integrated lens aligned to one end of the hole, and wherein the integrated optical waveguide structure of the photonics package comprises a vertical grating coupler that is disposed in alignment with another end of the hole, wherein light is transmitted through the hole in the application board between the integrated lens and the vertical grating coupler.

18. A method to construct a package structure, comprising;

fabricating, an integrated circuit chip comprising a silicon-on-insulator (SOI) substrate, wherein the SOI substrate comprises a bulk substrate layer, a buried oxide layer disposed on the bulk substrate layer, an active silicon layer disposed on the buried oxide layer, and a BEOL (back-end-of-line) structure formed over the active silicon layer, wherein the active silicon layer comprises an integrated optical waveguide structure;

bonding a first surface of an interposer substrate to the BEOL structure of the integrated circuit chip;

forming conductive through vias in the interposer substrate in alignment with contact pads of the BEOL structure, and forming contact pads on a second surface of the interposer substrate;

removing the bulk substrate layer;

forming one or more inverted pad structures through the buried oxide layer to buried pads in the BEOL structure;

forming solder bumps on the contact pads of the interposer substrate; and

mounting an optoelectronics device to the integrated circuit chip such that the optoelectronics device is electrically connected to one or more of the inverted pad structures and such that the optoelectronics device is in contact with a portion of the buried oxide layer and in alignment with at least a portion of the integrated optical waveguide structure.

19. The method of claim 18, further comprising depositing and patterning a capping layer on the buried oxide layer after the bulk substrate layer is removed.

20. The method of claim 18, further comprising bonding a waveguide core of a flexible polymer waveguide to a portion of the buried oxide layer in alignment with an end portion of the integrated optical waveguide structure, wherein the waveguide colt is adiabatically coupled to the end portion of the integrated optical waveguide structure through the buried oxide layer.