GATE WITH SELF-ALIGNED LEDGED FOR ENHANCEMENT MODE GaN TRANSISTORS

• US 20170047414A9
• Filed: 07/30/2014
• Published: 02/16/2017
• Est. Priority Date: 04/08/2009
• Status: Active Grant

• Current Assignee: Efficient Power Conversion Corporation
• Original Assignee: Efficient Power Conversion Corporation
• Inventors: Cao, Jianjun, Lidow, Alexander, Nakata, Alana
• Granted Patent: US 9,748,347 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/283 Deposition of conductive or insulating materials for electrodes conducting electric current
• CPC Class Codes: H01L 21/28587 characterised by the sectional shape, e.g. T, inverted T
• CPC Class Codes: H01L 29/1066 Gate region of field-effect devices with PN junction gate
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/205 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/42316 for field-effect transistors
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/7786 with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT

Abstract

An enhancement-mode GaN transistor with reduced gate leakage current between a gate contact and a 2DEG region and a method for manufacturing the same. The enhancement-mode GaN transistor including a GaN layer, a barrier layer disposed on the GaN layer with a 2DEG region formed at an interface between the GaN layer and the barrier layer, and source contact and drain contacts disposed on the barrier layer. The GaN transistor further includes a p-type gate material formed above the barrier layer and between the source and drain contacts and a gate metal disposed on the p-type gate material, with wherein the p-type gate material including comprises a pair of self-aligned ledges that extend toward the source contact and drain contact, respectively.

Claims

1. An enhancement-mode GaN transistor, comprising:

a GaN layer;

a barrier layer disposed on the GaN layer with a 2DEG region formed at an interface between the GaN layer and the barrier layer;

a p-type gate material formed above the barrier layer, the p-type gate material having side surfaces extending towards the barrier layer; and

a gate metal disposed on the p-type gate material, the gate metal having sidewalls extending towards the p-type gate material,

wherein the p-type gate material comprises a pair of horizontal ledges that extend past the respective sidewalls of the gate metal, the pair of horizontal edges having substantially equal widths from the sidewalls of the gate metal to the side surfaces of the p-type gate material, respectively.

2. The enhancement-mode GaN transistor according to claim 1, further comprising a source contact and a drain contact disposed on the barrier layer.

3. The enhancement-mode GaN transistor according to claim 2, wherein the pair of horizontal ledges of the p-type gate material extend toward the source contact and drain contact, respectively.

4. The enhancement-mode GaN transistor according to claim 3, wherein the side surfaces of the p-type gate material extend horizontally towards the source contact and drain contact, respectively, and contact the barrier layer.

5. The enhancement-mode GaN transistor according to claim 1, wherein the pair of horizontal ledges of the p-type gate material are self-aligned.

6. The enhancement-mode GaN transistor according to claim 1, wherein the barrier layer comprises aluminum gallium nitride (AlGaN).

7. The enhancement-mode GaN transistor according to claim 1, wherein the p-type gate material has a first width between the side surfaces of the p-type gate material and the gate metal has a second width between sidewalls of the gate metal, the second width being less than the first width.

8. An enhancement-mode GaN transistor, comprising:

a GaN layer;

a barrier layer disposed on the GaN layer with a 2DEG region formed at an interface between the GaN layer and the barrier layer;

a source contact and a drain contact disposed on the barrier layer;

a p-type gate material formed above the barrier layer and between the source and drain contacts;

and a gate metal disposed on the p-type gate material,

wherein the p-type gate material comprises a pair of self-aligned ledges that extend past sidewalls of the gate metal towards the source contact and drain contact, respectively.

9. The enhancement-mode GaN transistor according to claim 8, wherein the p-type gate material further comprises side surfaces extending horizontally towards the source contact and drain contact, respectively, and contacting the barrier layer.

10. The enhancement-mode GaN transistor according to claim 8, wherein the barrier layer comprises aluminum gallium nitride (AlGaN).

11. The enhancement-mode GaN transistor according to claim 8, wherein the pair of self-aligned ledges are symmetric with respect to the gate metal.

12. A method for manufacturing an enhancement-mode GaN transistor, the method comprising:

forming a GaN layer;

forming a barrier layer on the GaN layer;

depositing a p-type gate material on the barrier layer;

depositing a gate metal on the p-type gate material;

forming a photoresist over the gate metal;

etching the gate metal and the p-type gate material; and

isotropically etching the gate metal to form pair of ledges on the p-type gate material below the gate metal.

13. The method according to claim 12, wherein the step of isotropically etching the gate metal comprises etching the gate metal to reduce a width of the gate metal, such that the width of the gate metal is less than a width of the p-type gate material.

14. The method according to claim 12, further comprising depositing source and drain contacts on the barrier layer.

15. The method according to claim 12, wherein the step of etching the p-type material comprises forming side surfaces of the p-type gate material that extend horizontally towards the source contact and drain contact, respectively, and contact the barrier layer.

16. The method according to claim 12, wherein the pair of horizontal ledges of the p-type gate material are self-aligned.