Barrier Layer for Dielectric Layers in Semiconductor Devices

• US 20170047420A1
• Filed: 10/27/2016
• Published: 02/16/2017
• Est. Priority Date: 03/31/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Sheng-Wen, Lin, Yu-Ting, Chang, Che-Hao, You, Wei-Ming, Wang, Ting-Chun
• Granted Patent: US 10,453,933 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02247 formation by nitridation, e.g. nitridation of the substrate
• CPC Class Codes: H01L 21/0234 treatment by exposure to a plasma
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/28026 characterised by the conductor H01L21/28176 takes precedence
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/28176 with a treatment, e.g. annealing, after the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/321 After treatment
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/4941 with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66583 with initial gate mask or masking layer complementary to the prospective gate location, e.g. with dummy source and drain contacts
• CPC Class Codes: H01L 29/6659 : with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 : with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A semiconductor device having a high-k gate dielectric, and a method of manufacture, is provided. A gate dielectric layer is formed over a substrate. An interfacial layer may be interposed between the gate dielectric layer and the substrate. A barrier layer, such as a TiN layer, having a higher concentration of nitrogen along an interface between the barrier layer and the gate dielectric layer is formed. The barrier layer may be formed by depositing, for example, a TiN layer and performing a nitridation process on the TiN layer to increase the concentration of nitrogen along an interface between the barrier layer and the gate dielectric layer. A gate electrode is formed over the barrier layer.

Claims

1. A semiconductor device comprising:

a gate dielectric layer over a substrate;

a conductive layer over the gate dielectric layer, the conductive layer having a higher relative nitrogen concentration along a top surface than at a location away from the top surface;

a silicon cap over the conductive layer; and

a metal gate electrode over the conductive layer.

2. The semiconductor device of claim 1, wherein the conductive layer comprises a Ti_xN_y layer.

3. The semiconductor device of claim 2, wherein the Ti_xN_y layer comprises a ratio of y:

x of about 1.0 to about 1.2 along the top surface of the conductive layer.

4. The semiconductor device of claim 3, wherein the Ti_xN_y layer comprises a ratio of y:

x of about 0.85 to about 0.98 at a location away from the top surface of the conductive layer.

5. The semiconductor device of claim 1, further comprising gate spacers over the substrate and adjacent to the gate dielectric layer.

6. The semiconductor device of claim 5, further comprising an inter-layer dielectric over the substrate, the gate spacers and the metal gate electrode.

7. The semiconductor device of claim 6, further comprising:

source/drain regions in the substrate; and

a silicide region over each of the source/drain regions.

8. The semiconductor device of claim 1, further comprising an interfacial layer over the substrate.

9. The semiconductor device of claim 8, wherein the interfacial layer comprises an oxide layer.

10. A semiconductor device comprising:

a raised structure over a substrate, the raised structure comprising;

gate spacers;

a gate dielectric layer over the substrate, the gate dielectric layer having a first horizontal portion and first vertical portions, the first vertical portions adjacent to the gate spacers;

a conductive layer over the gate dielectric layer, the conductive layer having a second horizontal portion and second vertical portions, the second vertical portions adjacent to the first vertical portions of the gate dielectric layer, wherein a top surface of the second horizontal portion has a higher nitrogen concentration than a location of the second horizontal portion away from the top surface;

a silicon cap over the conductive layer; and

a gate electrode over the silicon cap;

a source/drain region on each side of the raised structure; and

a silicide region over each source/drain region.

11. The semiconductor device of claim 10, further comprising an interfacial layer over the substrate.

12. The semiconductor device of claim 11, wherein the interfacial layer comprises an oxide layer.

13. The semiconductor device of claim 12, further comprising spacers over the substrate and adjacent to the first vertical portions of the gate dielectric layer.

14. The semiconductor device of claim 13, further comprising:

an inter-layer dielectric over the substrate, the spacers, and the gate electrode; and

a contact through the inter-layer dielectric, the contact contacting the gate electrode.

15. The semiconductor device of claim 10, wherein the first vertical portions, the second vertical portions, and the gate electrode are level.

16. The semiconductor device of claim 10, wherein the conductive layer comprises a Ti_xN_y layer, the nitrogen to titanium concentrations in the top surface having a ratio y:

x of about 1.0 to about 1.2.

17. The semiconductor device of claim 15, wherein the conductive layer comprises a Ti_xN_y layer, the nitrogen to titanium concentrations in the location away from the top surface having a ratio y:

x of about 0.85 to about 0.98.

19. The semiconductor device of claim 17, further comprising an interfacial layer over the substrate.

20. The semiconductor device of claim 17, further comprising:

source/drain regions along a top surface of the substrate, the source/drain regions located on opposite sides of the dielectric layer;

silicide regions over the source/drain regions; and

sidewall spacers over the source/drain regions.

18. A semiconductor device comprising:

a substrate;

a dielectric layer over the substrate;

a barrier layer over the dielectric layer, the barrier layer comprising a first Ti_xN_y layer along a top surface of the barrier layer, a ratio of y;

x being from about 1.0 to about 1.2 at the first Ti_xN_y layer, and the barrier layer comprising a second Ti_xN_y layer at a location away from the top surface of the barrier layer, a ratio of y;

x of about 0.85 to about 0.98 at the second Ti_xN_y layer;

a silicon cap over the barrier layer;

a metal gate electrode over the barrier layer;

an inter-layer dielectric over the metal gate electrode; and

a contact through the inter-layer dielectric and over the metal gate electrode.