Integrated Circuit Structure with Substrate Isolation and Un-Doped Channel

• US 20170047432A1
• Filed: 10/31/2016
• Published: 02/16/2017
• Est. Priority Date: 09/29/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Guan-Lin, Ching, Kuo-Cheng
• Granted Patent: US 10,170,592 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

The present disclosure provides a method of fabricating a nonplanar circuit device. The method includes receiving a substrate having a first semiconductor layer of a first semiconductor material and a second semiconductor layer of a second semiconductor material on the first semiconductor layer, wherein the second semiconductor material is different from the first semiconductor material in composition. The method further includes patterning the first and second semiconductor layers to form a fin structure in the first and second semiconductor layers. The method further includes performing a selective oxidization process to the first semiconductor layer such that a bottom portion of the first semiconductor layer is oxidized.

Claims

1. A method of fabricating a nonplanar circuit device, the method comprising:

receiving a substrate having a first semiconductor layer of a first semiconductor material and a second semiconductor layer of a second semiconductor material on the first semiconductor layer, wherein the second semiconductor material is different from the first semiconductor material in composition;

patterning the first and second semiconductor layers to form a fin structure in the first and second semiconductor layers; and

performing a selective oxidization process to the first semiconductor layer such that a bottom portion of the first semiconductor layer is oxidized.

2. The method of claim 1, further comprising:

forming a dummy gate over a channel region of the fin structure;

removing the dummy gate, thereby resulting in a gate trench; and

performing a second selective oxidization process to the first semiconductor layer such that a top portion of the first semiconductor layer within the gate trench is oxidized and a substantial portion of the second semiconductor layer within the gate trench is not oxidized.

3. The method of claim 2, further comprising:

forming a gate structure in the gate trench.

4. The method of claim 2, further comprising:

recessing the fin structure in a source/drain region after the forming of the dummy gate; and

epitaxially growing a source/drain feature in the source/drain region before the removing of the dummy gate.

5. The method of claim 1, wherein the first semiconductor material includes silicon germanium and the second semiconductor material is primarily silicon.

6. The method of claim 1, after the performing of the selective oxidization process, further comprising:

depositing a dielectric material surrounding the fin structure; and

recessing the dielectric material such that the first semiconductor material is at least partially uncovered by the dielectric material.

7. The method of claim 6, after the performing of the selective oxidization process, further comprising:

forming a liner on top and sidewalls of the fin structure, wherein the dielectric material is deposited over the liner.

8. The method of claim 1, before the performing of the selective oxidization process, further comprising:

forming a liner on at least sidewalls of the fin structure, wherein the liner covers an upper portion of the first semiconductor layer; and

etching the first semiconductor layer to expose the bottom portion of the first semiconductor layer below the liner.

9. The method of claim 8, wherein the etching of the first semiconductor layer also etches the substrate, thereby exposing a portion of the substrate having a material different from the first semiconductor material in composition.

10. The method of claim 9, wherein the selective oxidization process oxidizes the bottom portion of the first semiconductor layer but not the portion of the substrate.

11. A method of fabricating a nonplanar circuit device, the method comprising:

receiving a substrate having a first semiconductor layer of a first semiconductor material and a second semiconductor layer of a second semiconductor material on the first semiconductor layer, wherein the second semiconductor material is different from the first semiconductor material in composition;

patterning the first and second semiconductor layers to form a fin structure in the first and second semiconductor layers;

forming a dummy gate over a channel region of the fin structure;

removing the dummy gate, thereby resulting in a gate trench; and

performing a selective oxidization process to the first semiconductor layer such that a top portion of the first semiconductor layer within the gate trench is oxidized and a substantial portion of the second semiconductor layer within the gate trench is not oxidized.

12. The method of claim 11, wherein the first semiconductor material includes silicon germanium and the second semiconductor material is un-doped silicon.

13. The method of claim 11, before the forming of the dummy gate, further comprising:

forming a liner on at least sidewalls of the fin structure;

etching the first semiconductor layer to expose a bottom portion of the first semiconductor layer below the liner; and

performing another selective oxidization process to the first semiconductor layer such that the bottom portion of the first semiconductor layer is oxidized.

14. The method of claim 13, further comprising:

depositing a dielectric material surrounding the fin structure; and

recessing the dielectric material such that the first semiconductor material is at least partially uncovered by the dielectric material, wherein the dummy gate is formed over the dielectric material.

15. The method of claim 11, before the removing of the dummy gate, further comprising:

recessing the fin structure in a source/drain region;

epitaxially growing a source/drain feature in the source/drain region; and

depositing an inter-level dielectric material over the source/drain feature and surrounding the dummy gate.

16. The method of claim 11, wherein the selective oxidization process does not oxidize portions of the substrate within the gate trench and below the first semiconductor layer.

17. A method of fabricating a nonplanar circuit device, the method comprising:

receiving a substrate having a first semiconductor layer of a first semiconductor material and a second semiconductor layer of a second semiconductor material on the first semiconductor layer, wherein the second semiconductor material is different from the first semiconductor material in composition;

patterning the first and second semiconductor layers to form a fin structure in the second semiconductor layer;

performing a first selective oxidization process to the first semiconductor layer such that a bottom portion of the first semiconductor layer is oxidized;

forming a dummy gate over a channel region of the fin structure;

removing the dummy gate, thereby resulting in a gate trench; and

performing a second selective oxidization process to the first semiconductor layer such that a top portion of the first semiconductor layer within the gate trench is oxidized.

18. The method of claim 17, wherein the first semiconductor material includes silicon germanium and the second semiconductor material is silicon.

19. The method of claim 17, wherein each of the first and second selective oxidization processes is designed to selectively oxidize the first semiconductor material without oxidizing the second semiconductor material.

20. The method of claim 17, further comprising:

forming a gate structure in the gate trench.