SEMICONDUCTOR DEVICE

• US 20170047440A1
• Filed: 08/01/2016
• Published: 02/16/2017
• Est. Priority Date: 08/11/2015
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: OHASHI, Teruyuki, llJIMA, Ryosuke
• Granted Patent: US 10,586,862 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/0465 using masks
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device according to embodiments includes, a SiC substrate, SiC layer, a trench having a side face and a bottom face, a first conductivity type first SiC region, a second conductivity type second SiC region between the first SiC region and the SiC substrate, a first conductivity type third SiC region between the second SiC region and the SiC substrate, a boundary between the second SiC region and the third SiC region provided at a side of the side face, the boundary including a first region, a distance between the first region and a front face of the SiC layer increasing as a distance from the side face to the first region increasing, and distance from the side face to the first region being 0 μm or more and 0.3 μm or less, a gate insulating film and gate insulating film.

Claims

1. A semiconductor device, comprising:

a SiC substrate;

a SiC layer provided on the SiC substrate, the SiC layer including a first trench at a side of front face of the SiC layer, the first trench including a side face and a bottom face;

a first conductivity type first SiC region provided in the SiC layer;

a second conductivity type second SiC region provided between the first SiC region and the SiC substrate in the SiC layer;

a first conductivity type third SiC region provided between the second SiC region and the SiC substrate in the SiC layer, a boundary between the second SiC region and the third SiC region disposed at a side of the side face of the first trench, the boundary including a first region, a distance between the first region and the front face of the SiC layer increasing as a distance from the side face of the first trench to the first region increasing, a distance between the side face of the first trench to an end of the first region close to the first trench being 0 μ

m or more and 0.3 μ

m or less;

a gate insulating film provided on the side face and the bottom face of the first trench; and

a gate electrode, the gate insulating film disposed between the gate electrode and the first SiC region, the second SiC region, and the third SiC region.

2. The device according to claim 1, wherein the first region contacts with the side face of the first trench.

3. The device according to claim 1, wherein the boundary includes a second region substantially parallel to the front face of the SiC layer, the second region is provided between the first region and the first trench, and the second region contacts with the side face of the first trench.

4. The device according to claim 1, wherein the first region has a first inclination angle with respect to the front face, and the first inclination angle is 15°

or more and 70°

or less.

5. The device according to claim 1, wherein the first region has a first inclination angle with respect to the front face, and the first inclination angle is 15°

or more and 60°

or less.

6. The device according to claim 1, wherein the boundary includes a third region substantially parallel to the front face, and the first region is provided between the third region and the first trench.

7. The device according to claim 1, wherein the boundary includes a fourth region substantially perpendicular to the front face, and the first region is provided between the fourth region and the first trench.

8. The device according to claim 1, wherein the gate insulating film is an oxide film.

9. The device according to claim 1, wherein a film thickness of the gate insulating film on the bottom face of the first trench is thicker than a film thickness of the gate insulating film on the side face of the first trench.

10. The device according to claim 1, further comprising a second conductivity type fourth SiC region provided on a side of the first SiC region in the SiC layer, the fourth SiC region having higher second conductivity type impurity concentration than that of the second SiC region.

11. The device according to claim 1, further comprising a second conductivity type fifth SiC region provided between the bottom face of the first trench and the third SiC region in the SiC layer, the fifth SiC region being in contact with the bottom face.

12. The device according to claim 1, further comprising a first electrode and a second electrode, the SiC layer and the SiC substrate provided between the first electrode and the second electrode,

wherein the SiC layer includes a second trench at the side of front face of the SiC layer, the first SiC region is provided between the first trench and the second trench, and at least a part of the first electrode is disposed in the second trench.

13. The device according to claim 12, further comprising a second conductivity type fourth SiC region provided between a bottom face of the second trench and the third SiC region in the SiC layer, the fourth SiC region having higher second conductivity type impurity concentration than that of the second SiC region.

14. The device according to claim 1, wherein an interior angle of the second SiC region at the boundary is 90°

or more.

15. The device according to claim 1, wherein the boundary does not includes a bending portion with an angle of 90°

or less.

16. The device according to claim 1, wherein the first conductivity type is an n-type.

17. The device according to claim 1, wherein the SiC substrate is a first conductivity type.

18. The device according to claim 1, wherein the SiC substrate is a second conductivity type.

19. A semiconductor device, comprising:

a SiC substrate;

a SiC layer provided on the SiC substrate, the SiC layer including a first trench at a side of front face of the SiC layer, the first trench including a side face and a bottom face;

a first conductivity type first SiC region provided in the SiC layer;

a second conductivity type second SiC region provided between the first SiC region and the SiC substrate in the SiC layer;

a first conductivity type third SiC region provided between the second SiC region and the SiC substrate in the SiC layer, a boundary between the second SiC region and the third SiC region disposed at a side of the side face of the first trench, the boundary including a first region, the first region having a first position and a second position, the first position being closer to the first trench than the second position, a distance between the second position and the front face of the SiC layer being larger than a distance between the first position and the front face of the SiC layer, a distance between the side face of the first trench to an end of the first region close to the first trench being 0 μ

m or more and 0.3 μ

m or less;

a gate insulating film provided on the side face and the bottom face of the first trench; and

a gate electrode, the gate insulating film disposed between the gate electrode and the first SiC region, the second SiC region, and the third SiC region.

20. A semiconductor device, comprising:

a SiC substrate;

a SiC layer provided on the SiC substrate, the SiC layer including a first trench at a side of front face of the SiC layer, the first trench including a side face and a bottom face;

a first conductivity type first SiC region provided in the SiC layer;

a second conductivity type second SiC region provided between the first SiC region and the SiC substrate in the SiC layer;

a first conductivity type third SiC region provided between the second SiC region and the SiC substrate in the SiC layer, a boundary between the second SiC region and the third SiC region disposed at a side of the side face of the first trench, the boundary including a first region, the first region having a first position and a second position, the first position being closer to the first trench than the second position, a distance between the second position and a back face of the SiC substrate being smaller than a distance between the first position and the back face of the SiC substrate, a distance between the side face of the first trench to an end of the first region close to the first trench being 0 μ

m or more and 0.3 μ

m or less;

a gate insulating film provided on the side face and the bottom face of the first trench; and

a gate electrode, the gate insulating film disposed between the gate electrode and the first SiC region, the second SiC region, and the third SiC region.