INTERNAL SPACERS FOR NANOWIRE TRANSISTORS AND METHOD OF FABRICATION THEREOF

• US 20170047452A1
• Filed: 10/26/2016
• Published: 02/16/2017
• Est. Priority Date: 10/03/2013
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Intel Corporation
• Inventors: Kim, Seiyon, Simon, Daniel A., Rahhal-Orabi, Nadia M., Lim, Chul-Hyun, Kuhn, Kelin J.
• Granted Patent: US 9,935,205 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/02603 Nanowires
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0669 Nanowires or nanotubes carbon nanotubes as material of solid-state device active part H10K85/211
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78618 : characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78651 : Silicon transistors H01L29/78606 - H01L29/78645 take precedence
• CPC Class Codes: H01L 29/78684 : having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A nanowire transistor of the present description may be produced with internal spacers formed by using sacrificial spacers during the fabrication thereof. Once the nanowire transistor is formed, the sacrificial spacers, which are position between the transistor gate and the source and drains (respectively), may be removed. The sacrificial material between channel nanowires of the nanowire transistor may then be removed and a dielectric material may be deposited to fill the spaces between the channel nanowires. The dielectric material not between the channel nanowires may be removed to form the internal spacers. External spacers, which are position between the transistor gate and the source and drains (respectively), may then be formed adjacent the internal spacers and transistor channel nanowires.

Claims

1. A microelectronic structure having:

a fin structure, having a plurality of channel nanowires, disposed on a substrate;

a gate structure abutting a portion of the fin structure, wherein the gate structure comprises a gate dielectric surrounding each of the plurality of the channel nanowires in the fin structure and a gate electrode abutting the gate dielectric; and

a dielectric material spacer adjacent one end of the gate electrode, wherein the spacer abuts a portion of the fin structure that comprises the channel nanowires and wherein a portion of the spacer is disposed between the channel nanowires.

2. The microelectronic structure of claim 1, wherein the dielectric material spacer comprises a low-k dielectric material.

3. The microelectronic structure of claim 1, wherein the channel nanowires comprise silicon germanium.

4. The microelectronic structure of claim 1, wherein the channel nanowires comprise silicon.

5. The microelectronic structure of claim 1, further comprising one of a source and a drain abutting one end of the fin structure and the dielectric material spacer;

6. A microelectronic structure having:

a fin structure, having a plurality of channel nanowires, disposed on a substrate;

a gate structure abutting a portion of the fin structure, wherein the gate structure comprises a gate dielectric surrounding each of the plurality of the channel nanowires in the fin structure and a gate electrode abutting the gate dielectric;

internal dielectric material spacers disposed between the channel nanowires; and

an external dielectric material spacer abutting the internal spacers and abutting the channel nanowires.

7. The microelectronic structure of claim 6, wherein the external dielectric material spacer comprises a dielectric material that is different from that of the internal dielectric material spacers.

8. The microelectronic structure of claim 6, wherein the internal dielectric material spacers comprise a low-k dielectric material.

9. The microelectronic structure of claim 6, wherein the external dielectric material spacer comprises a low-k dielectric material.

10. The microelectronic structure of claim 6, wherein the channel nanowires comprise silicon germanium.

11. The microelectronic structure of claim 6, wherein the channel nanowires comprise silicon.

12. The microelectronic structure of claim 6, further comprising one of a source and a drain abutting one end of the fin structure, the internal dielectric material spacers, and the external dielectric material spacer.