INTERNAL SPACERS FOR NANOWIRE TRANSISTORS AND METHOD OF FABRICATION THEREOF
First Claim
1. A microelectronic structure having:
- a fin structure, having a plurality of channel nanowires, disposed on a substrate;
a gate structure abutting a portion of the fin structure, wherein the gate structure comprises a gate dielectric surrounding each of the plurality of the channel nanowires in the fin structure and a gate electrode abutting the gate dielectric; and
a dielectric material spacer adjacent one end of the gate electrode, wherein the spacer abuts a portion of the fin structure that comprises the channel nanowires and wherein a portion of the spacer is disposed between the channel nanowires.
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Accused Products
Abstract
A nanowire transistor of the present description may be produced with internal spacers formed by using sacrificial spacers during the fabrication thereof. Once the nanowire transistor is formed, the sacrificial spacers, which are position between the transistor gate and the source and drains (respectively), may be removed. The sacrificial material between channel nanowires of the nanowire transistor may then be removed and a dielectric material may be deposited to fill the spaces between the channel nanowires. The dielectric material not between the channel nanowires may be removed to form the internal spacers. External spacers, which are position between the transistor gate and the source and drains (respectively), may then be formed adjacent the internal spacers and transistor channel nanowires.
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Citations
12 Claims
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1. A microelectronic structure having:
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a fin structure, having a plurality of channel nanowires, disposed on a substrate; a gate structure abutting a portion of the fin structure, wherein the gate structure comprises a gate dielectric surrounding each of the plurality of the channel nanowires in the fin structure and a gate electrode abutting the gate dielectric; and a dielectric material spacer adjacent one end of the gate electrode, wherein the spacer abuts a portion of the fin structure that comprises the channel nanowires and wherein a portion of the spacer is disposed between the channel nanowires. - View Dependent Claims (2, 3, 4, 5)
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6. A microelectronic structure having:
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a fin structure, having a plurality of channel nanowires, disposed on a substrate; a gate structure abutting a portion of the fin structure, wherein the gate structure comprises a gate dielectric surrounding each of the plurality of the channel nanowires in the fin structure and a gate electrode abutting the gate dielectric; internal dielectric material spacers disposed between the channel nanowires; and an external dielectric material spacer abutting the internal spacers and abutting the channel nanowires. - View Dependent Claims (7, 8, 9, 10, 11, 12)
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Specification