Tracing Interconnect Circuitry

• US 20170052868A1
• Filed: 08/19/2016
• Published: 02/23/2017
• Est. Priority Date: 08/21/2015
• Status: Active Grant

• Current Assignee: Siemens Industry Software Inc. (Siemens AG)
• Original Assignee: UltraSoC Technologies Ltd (Siemens AG)
• Inventors: Robertson, Iain Craig, Hopkins, Andrew Brian Thomas, Thyer, Michael Jonathan
• Granted Patent: US 10,437,700 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/3041 where the computing system component is an input/output interface interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units G06F13/00
• CPC Class Codes: G06F 11/3471 Address tracing
• CPC Class Codes: G06F 11/3485 for I/O devices
• CPC Class Codes: G06F 11/349 for interfaces, buses
• CPC Class Codes: G06F 11/364 tracing values on a bus
• CPC Class Codes: G06F 2201/87 Monitoring of transactions

Abstract

A method of tracing transactions on an integrated circuit chip. The method comprises, for each transaction: extracting the transaction from interconnect circuitry of the integrated circuit chip, the transaction comprising an address signal and a data signal; applying a filtering condition to the address signal; only if the address signal does not fail the filtering condition, storing the address signal in an address trace buffer; storing the data signal in a data trace buffer; applying a triggering condition to the stored transaction; and outputting the stored transaction if the stored transaction matches the triggering condition.

Claims

1. A method of tracing transactions on an integrated circuit chip, the method comprising, for each transaction:

extracting the transaction from interconnect circuitry of the integrated circuit chip, the transaction comprising an address signal and a data signal;

applying a filtering condition to the address signal;

only if the address signal does not fail the filtering condition, storing the address signal in an address trace buffer;

storing the data signal in a data trace buffer;

applying a triggering condition to the stored transaction; and

outputting the stored transaction if the stored transaction matches the triggering condition.

2. A method as claimed in claim 1, wherein the transaction further comprises a response signal, the method further comprising storing the response signal in a response trace buffer.

3. A method as claimed in claim 1, comprising, following extracting the transaction from the interconnect circuitry, if the address signal fails the filtering condition, discarding the address signal.

4. A method as claimed in claim 1, comprising, following extracting the transaction from the interconnect circuitry, if the address signal fails the filtering condition, discarding the transaction.

5. A method as claimed in claim 1, comprising, if the stored transaction matches the triggering condition, outputting all contents of the address trace buffer and data trace buffer.

6. A method as claimed in claim 1, comprising, if the stored transaction does not match the triggering condition, retaining the stored transaction in the trace buffers.

7. A method as claimed in claim 2, comprising:

upon becoming full, overwriting the address trace buffer,

upon becoming full, overwriting the data trace buffer, and

upon becoming full, overwriting the response trace buffer.

8. A method as claimed in claim 1, further comprising:

applying the filtering condition to the data signal; and

only if the data signal does not fail the filtering condition, storing the data signal in the data trace buffer.

9. A method as claimed in claim 8, comprising, if the data signal fails the filtering condition, discarding all constituents of the transaction not already stored.

10. A method as claimed in claim 2, further comprising:

applying the filtering condition to the response signal; and

only if the response signal does not fail the filtering condition, storing the response signal in the response trace buffer.

11. A method as claimed in claim 1, further comprising:

allocating a tracker identity in association with the address signal; and

allocating the tracker identity in association with the data signal.

12. A method as claimed in claim 11, comprising following outputting the stored transaction, reassembling the transaction by aggregating the address signal and data signal stored in association with the same tracker identity.

13. A method as claimed in claim 1, wherein the transactions are communicated according to a protocol in which a data signal of a transaction is permitted to precede the address signal of the transaction by a time T, the method further comprising after extracting the transaction from the interconnect circuitry, pre-buffering the data signal prior to storing the data signal in the data trace buffer for at least the time T.

14. A method as claimed in claim 13, further comprising only outputting the pre-buffered data signal to the data trace buffer if the address signal of the transaction did not fail the address filtering condition.

15. A method as claimed in claim 13, comprising discarding the pre-buffered data signal if the address signal of the transaction fails the address filtering condition.

16. A method as claimed in claim 2, comprising:

applying a timestamp to the address signal on the address signal entering the address trace buffer,

applying a timestamp to the data signal on the data signal entering the data trace buffer, and

applying a timestamp to the response signal on the response signal entering the response trace buffer.

17. A method as claimed in claim 1, wherein the triggering condition is a transaction error, a specific address signal, or a transaction in a specific address range.

18. An integrated circuit chip comprising:

system circuitry comprising interconnect circuitry configured to transport transactions, each transaction comprising an address signal and a data signal; and

debugging circuitry comprising an address trace buffer and a data trace buffer, the debugging circuitry being configured to;

extract a transaction from the interconnect circuitry;

apply an address filtering condition to the address signal;

only if the address signal does not fail the address filtering condition,

store the address signal in the address trace buffer;

store the data signal in the data trace buffer;

apply a triggering condition to the stored transaction; and

output the stored transaction if the stored transaction matches the triggering condition.

19. An integrated circuit chip as claimed in claim 18, wherein the address trace buffer and the data trace buffer are each at least as long as the maximum number of concurrent transactions on the interconnect circuitry.

20. An integrated circuit chip as claimed in claim 18, wherein the interconnect circuitry is a bus.