MODEL-BASED RULE TABLE GENERATION

• US 20170053058A1
• Filed: 08/21/2015
• Published: 02/23/2017
• Est. Priority Date: 08/21/2015
• Status: Abandoned Application

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chou, Shuo-Yen, Yu, Jue-Chin
• Application Number:
  US14/832,884
• Publication Number:
  US 20170053058A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G03F 1/36 Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

Provided is a method for fabricating a semiconductor device including receiving an integrated circuit (IC) layout pattern, for example, from a design house. In some embodiments, a process simulation model is utilized to generate a freeform layout pattern by an inverse lithography technology (ILT) process. The process simulation model is configured to simulate processing conditions for the IC layout pattern. In various embodiments, the freeform layout pattern is associated with the IC layout pattern. In some examples, a simplified layout pattern is generated, where the simplified layout pattern is an approximation of the freeform layout pattern. Thereafter, sub-resolution assist feature (SRAF) rules, based on the simplified layout pattern, may be calculated and an SRAF rule table may be generated.

Claims

1. A method of semiconductor device fabrication, comprising:

receiving an integrated circuit (IC) layout pattern;

utilizing a process simulation model configured to simulate processing conditions for the IC layout pattern, generating a second layout pattern by a model-based (MB) mask correction process, wherein the second layout pattern is associated with the IC layout pattern;

generating a third layout pattern that is an approximation of the second layout pattern; and

calculating sub-resolution assist feature (SRAF) rules based on the third layout pattern.

2. The method of claim 1, wherein the generating the second layout pattern by the MB mask correction process includes generating the second layout pattern by an inverse lithography technology (ILT) process.

3. The method of claim 1, wherein the calculating the SRAF rules further includes calculating the SRAF rules based on the process simulation model.

4. The method of claim 1, wherein the second layout pattern includes a freeform layout pattern, and wherein the third layout pattern includes a simplified pattern.

5. The method of claim 1, wherein the third layout pattern includes a plurality of user-defined shapes, and wherein the plurality of user-defined shapes include one or more selected from a square, a rectangle, and an ellipse.

6. The method of claim 1, wherein the generating the third layout pattern includes performing a pattern simplification process to generate the third layout pattern.

7. The method of claim 1, further comprising updating an SRAF rule table.

8. The method of claim 7, wherein the SRAF rule table includes a model-based rule table (MBRT), and wherein the MBRT includes rule configurations for the third layout pattern.

9. The method of claim 8, wherein the SRAF rule table is a hybrid rule table, and wherein the hybrid rule table includes a rule-based rule table and the model-based rule table (MBRT).

10. The method of claim 1, further comprising:

identifying a layout hotspot within the received IC layout pattern; and

utilizing the process simulation model configured to simulate processing conditions for the identified layout hotspot, generating the second layout pattern by the ILT process, wherein the second layout pattern is associated with the layout hotspot.

11. The method of claim 1, further comprising:

after calculating the SRAF rules, transmitting a modified IC layout pattern to a mask fabricator, wherein the modified IC layout pattern includes modifications corresponding to the calculated SRAF rules, and fabricating a mask based on the modified IC layout pattern.

12. A method of semiconductor device fabrication, comprising:

performing an inverse lithography technology (ILT) process to generate a freeform layout pattern;

utilizing a process simulation model, and based on a plurality of manufacturing constraints, determining a simplified layout pattern corresponding to the freeform layout pattern;

extracting a plurality of rules from the simplified layout pattern; and

generating a rule table based on the extracted plurality of rules.

13. The method of claim 12, wherein the freeform layout pattern corresponds to a layout hotspot.

14. The method of claim 12, wherein the rule table includes a sub-resolution assist feature (SRAF) rule table, and wherein the SRAF rule table provides rule configurations for a plurality of user-define shapes.

15. The method of claim 12, wherein the performing the ILT process to generate the freeform layout pattern includes utilizing the process simulation model to generate a particular freeform layout pattern that conforms to a plurality of process constraints defined by the process simulation model.

16. The method of claim 12, wherein the performing the ILT process, the determining the simplified layout pattern, the extracting the plurality of rules, and the generating the rule table are performed by a mask design system executing software instructions within a processor of the mask design system.

17. The method of claim 12, further comprising:

fabricating a mask including a mask pattern based on the generated rule table; and

transferring the mask pattern to a semiconductor wafer to fabricate an integrated circuit (IC) device on the semiconductor wafer.

18. A method, comprising:

receiving an integrated circuit (IC) design layout;

identifying, by a mask design system, at least one layout hotspot in the received IC design layout;

generating, by the mask design system, an inverse lithography technology (ILT)-generated layout pattern corresponding to the identified at least one layout hotspot;

performing, by the mask design system, a layout simplification process to generate a simplified layout pattern corresponding to the ILT-generated layout pattern;

and

calculating, by the mask design system, sub-resolution assist feature (SRAF) rules based on the generated simplified layout pattern.

19. The method of claim 18, further comprising generating an SRAF rule table based on the calculated SRAF rules.

20. The method of claim 18, further comprising:

identifying, by the mask design system, another layout hotspot in the received IC design layout, wherein the another layout hotspot includes the same pattern as the at least one layout hotspot; and

applying, to the another layout hotspot, the same generated simplified layout pattern and calculated SRAF rules used for the at least one layout hotspot, wherein the applying includes inserting, to the another layout hotspot, an SRAF based on the calculated SRAF rules.