SEMICONDUCTOR MEMORY DEVICE AND STRUCTURE

• US 20170053906A1
• Filed: 08/22/2016
• Published: 02/23/2017
• Est. Priority Date: 08/23/2015
• Status: Active Grant

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Han, Jin-Woo
• Granted Patent: US 11,956,952 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/749 with turn-on by field effect
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/50 characterised by the boundary region between the core region and the peripheral circuit region
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions
• CPC Class Codes: H10B 63/20 comprising selection components having two electrodes, e.g. diodes
• CPC Class Codes: H10B 63/845 the switching components being connected to a common vertical conductor

Abstract

A device, including: a first structure including first memory cells, the first memory cells including first transistors; and a second structure including second memory cells, the second memory cells including second transistors, where the second transistors overlay the first transistors, and a plurality of memory cells control lines, where the first transistors are self-aligned to the second transistors, where a second transistor channel of the second transistors is aligned to a first transistor channel of the first transistors, the aligned is at an atomic level as would have been resulted from an epitaxial growth process.

Claims

1. A device, comprising:

a first structure comprising first memory cells, said first memory cells comprising first transistors; and

a second structure comprising second memory cells, said second memory cells comprising second transistors,

wherein said second transistors overlay said first transistors, and

a plurality of memory cells control lines,

wherein said first transistors are self-aligned to said second transistors,

wherein a second transistor channel of said second transistors is aligned to a first transistor channel of said first transistors, said aligned is at an atomic level as would have been resulted from an epitaxial growth process,

wherein said second structure comprises a vertically oriented transistor, and

wherein a second memory control line for said second memory cells is isolated from a first memory control line for said first memory cells.

2. The device according to claim 1,

wherein at least one of said first transistors comprises a drain and at least one of said second transistors comprises a source, and

wherein said drain is directly connected to said source.

3. The device according to claim 1,

wherein said second transistors comprise a drain and a source, and

wherein said drain and said source each have an ohmic connection to at least one of said a memory control lines.

4. The device according to claim 1, further comprising:

memory decoder circuits,

wherein said circuits are underlying said first structure or overlying said second structure.

5. The device according to claim 1,

wherein said memory control lines comprise horizontal transistors.

6. The device according to claim 1,

wherein said second transistors comprise SiGe material.

7. A device, comprising:

a first structure comprising first memory cells, said first memory cells comprising first transistors; and

a second structure comprising second memory cells, said second memory cells comprising second transistors,

wherein said second transistors overlay said first transistors, and

wherein said first transistors are self-aligned to said second transistors,

wherein a second transistor channel of said second transistors is aligned to a first transistor channel of said first transistors, said aligned is at an atomic level as would have been resulted from an epitaxial growth process,

wherein said first transistors and said second transistors each comprise a drain and a source, and

wherein at least one of said first transistor drains is directly connected to at least one of said second transistor sources.

8. The device according to claim 7,

wherein a second memory control line for said second memory cells is isolated from a first memory control line for said first memory cells.

9. The device according to claim 7,

wherein said second transistors comprise a drain and a source, and

wherein said drain and said source each have an ohmic connection to at least one of a plurality of memory control lines.

10. The device according to claim 7, further comprising:

memory decoder circuits,

wherein said circuits are underlying said first structure or overlying said second structure.

11. The device according to claim 7,

wherein said second memory cells comprise floating body memory cells.

12. The device according to claim 7, further comprising:

a memory peripheral circuit,

wherein said memory cells overlay at least a portion of said memory peripheral circuit.

13. The device according to claim 7, further comprising:

a plurality of memory control lines,

wherein said plurality of memory control lines comprises horizontal transistors.

14. A device, comprising:

a first structure comprising first memory cells, said first memory cells comprising first transistors; and

a second structure comprising second memory cells, said second memory cells comprising second transistors,

wherein said second transistors overlay said first transistors, and

wherein said first transistors are self-aligned to said second transistors,

wherein a second transistor channel of said second transistors is aligned to a first transistor channel of said first transistors, said aligned is at an atomic level as would have been resulted from an epitaxial growth process,

wherein said second structure comprises vertical oriented transistors,

wherein said device comprises a plurality of memory control lines,

wherein said second transistors comprise a drain and a source, and

wherein said drain and said source each have an ohmic connection to at least one of a plurality of memory control lines.

15. The device according to claim 14,

wherein said first transistors comprise a first drain, and

wherein said first drain is directly connected to said second transistor source.

16. The device according to claim 14,

wherein a second memory control line for said second memory cells is isolated from a first memory control line for said first memory cells.

17. The device according to claim 14, further comprising:

memory decoder circuits,

wherein said circuits are underlying said first structure or overlying said second structure.

18. The device according to claim 14,

said plurality of memory control lines comprises horizontal transistors.

19. The device according to claim 14,

wherein said second transistors comprise SiGe material.

20. The device according to claim 14,

wherein at least a portion of said plurality of memory control lines is silicided.