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SEMICONDUCTOR MEMORY DEVICE AND STRUCTURE

  • US 20170053906A1
  • Filed: 08/22/2016
  • Published: 02/23/2017
  • Est. Priority Date: 08/23/2015
  • Status: Active Grant
First Claim
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1. A device, comprising:

  • a first structure comprising first memory cells, said first memory cells comprising first transistors; and

    a second structure comprising second memory cells, said second memory cells comprising second transistors,wherein said second transistors overlay said first transistors, anda plurality of memory cells control lines,wherein said first transistors are self-aligned to said second transistors,wherein a second transistor channel of said second transistors is aligned to a first transistor channel of said first transistors, said aligned is at an atomic level as would have been resulted from an epitaxial growth process,wherein said second structure comprises a vertically oriented transistor, andwherein a second memory control line for said second memory cells is isolated from a first memory control line for said first memory cells.

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