SEMICONDUCTOR MEMORY DEVICE
First Claim
1. A semiconductor memory device comprising:
- a memory cell array having a multilayer stacked structure; and
a peripheral circuit configured to drive the memory cell array,wherein the peripheral circuit comprises a power decoupling capacitor circuit configured to provide decoupling capacitors to the memory cell array and the peripheral circuit,wherein the power decoupling capacitor circuit comprises;
conductive lines alternately stacked on top of one another;
a plurality of semiconductor pillars configured to pass through the conductive lines;
a horizontal connector configured to connect the semiconductor pillars to each other; and
a vertical connector configured to pass through the conductive lines and insulated from the horizontal connector.
1 Assignment
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Accused Products
Abstract
Provided herein is a semiconductor memory device including: a memory cell array having a multilayer stacked structure; and a peripheral circuit configured to drive the memory cell array. The peripheral circuit includes a power decoupling capacitor circuit configured to provide decoupling capacitors to the memory cell array and the peripheral circuit. The power decoupling capacitor circuit includes conductive lines which are alternately stacked on top of one another, a plurality of semiconductor pillars configured to pass through the conductive lines, a horizontal connector configured to connect the semiconductor pillars to each other, and a vertical connector configured to pass through the conductive lines and insulated from the horizontal connector.
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Citations
20 Claims
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1. A semiconductor memory device comprising:
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a memory cell array having a multilayer stacked structure; and a peripheral circuit configured to drive the memory cell array, wherein the peripheral circuit comprises a power decoupling capacitor circuit configured to provide decoupling capacitors to the memory cell array and the peripheral circuit, wherein the power decoupling capacitor circuit comprises; conductive lines alternately stacked on top of one another; a plurality of semiconductor pillars configured to pass through the conductive lines; a horizontal connector configured to connect the semiconductor pillars to each other; and a vertical connector configured to pass through the conductive lines and insulated from the horizontal connector. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A semiconductor memory device comprising:
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a semiconductor substrate including a cell region and a peripheral circuit region; conductive lines stacked on top of one another in the cell region and the peripheral circuit region; a plurality of semiconductor pillars configured to pass through the conductive lines; a horizontal connector configured to connect the semiconductor pillars that are disposed in the peripheral circuit region; and a vertical connector configured to pass through the conductive lines that are disposed in the peripheral circuit region, the vertical connector being insulated from the horizontal connector. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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19. A method of forming a power decoupling capacitor circuit, the comprising:
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providing conductive lines stacked on top of one another in at least a peripheral circuit region; providing a plurality of semiconductor pillars configured to pass through the conductive lines; connecting the semiconductor pillars to each other with a horizontal connector; and providing a vertical connector configured to pass through the conductive lines and insulated from the horizontal connector. - View Dependent Claims (20)
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Specification