SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

• US 20170054071A1
• Filed: 08/10/2016
• Published: 02/23/2017
• Est. Priority Date: 08/20/2015
• Status: Active Grant

• Current Assignee: ROHM Co., Ltd.
• Original Assignee: ROHM Co., Ltd.
• Inventors: TAKEDA, Hirofumi, KIMOTO, Satoshi
• Granted Patent: US 10,460,989 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G01R 33/0005 Geometrical arrangement of magnetic sensor elements; Apparatus combining different magnetic sensor types G01R33/0206 takes precedence
• CPC Class Codes: G01R 33/0076 Protection, e.g. with housings against stray fields
• CPC Class Codes: G01R 33/0206 Three-component magnetometers
• CPC Class Codes: H01L 21/76873 for electroplating
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 2924/15156 Side view
• CPC Class Codes: H01L 33/62 Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Abstract

A semiconductor device includes a semiconductor element, a semiconductor substrate on which the semiconductor element is mounted, a conductive layer formed on the substrate, and a sealing resin covering the semiconductor element. The substrate is formed with a recess receding from a main surface of the substrate and including a bottom surface and first and second sloped surfaces spaced apart from each other in a first direction perpendicular to the thickness direction of the substrate. The conductive layer includes first conduction paths on the first sloped surface, second conduction paths on the second sloped surface and bottom conduction paths on the bottom surface. The second sloped surface includes exposed regions line-symmetrical to the first conduction paths with respect to a line perpendicular to both the thickness direction of the substrate and the first direction, and the second conduction paths are not disposed at the exposed regions.

Claims

1. A semiconductor device comprising:

a semiconductor element;

a semiconductor substrate on which the semiconductor element is mounted, the substrate having a main surface;

a conductive layer formed on the substrate; and

a sealing resin covering the semiconductor element,

wherein the substrate is formed with a recess receding from the main surface, the recess including a bottom surface and first and second sloped surfaces spaced apart from each other in a first direction perpendicular to a thickness direction of the substrate,

the conductive layer includes first conduction paths on the first sloped surface, second conduction paths on the second sloped surface and bottom conduction paths on the bottom surface,

the second sloped surface includes a plurality of regions that are line-symmetrical to the first conduction paths with respect to an imaginary line parallel to a second direction perpendicular to both the thickness direction of the substrate and the first direction, and the plurality of regions are without the second conduction paths.

2. The semiconductor device according to claim 1, wherein each of the first and the second conduction paths is parallel to the first direction.

3. The semiconductor device according to claim 2, wherein each of the bottom conduction paths includes a portion extending parallel to the second direction.

4. The semiconductor device according to claim 3, wherein the bottom conduction paths are in contact with an intersection between the bottom surface and the first or second sloped surface.

5. The semiconductor device according to claim 1, wherein the conductive layer further includes pads formed on the bottom surface and electrically connected to the bottom conduction paths, and the semiconductor element is mounted on the pads.

6. The semiconductor device according to claim 1, wherein the conductive layer further includes terminals formed on the main surface and electrically connected to the first or second conduction path.

7. The semiconductor device according to claim 1, wherein the conductive layer includes a seed layer and a plated layer stacked on each other, and the seed layer is interposed between the substrate and the plated layer.

8. The semiconductor device according to claim 7, wherein the plated layer is thicker than the seed layer.

9. The semiconductor device according to claim 8, wherein the seed layer and the plated layer are both made of Cu.

10. The semiconductor device according to claim 1, wherein the first and the second sloped surfaces are inclined at a same angle with respect to the bottom surface.

11. The semiconductor device according to claim 1, wherein the bottom surface is orthogonal to the thickness direction of the substrate.

12. The semiconductor device according to claim 1, wherein the substrate includes a pair of first side faces spaced apart from each other in the first direction and a pair of second side faces spaced apart from each other in the second direction, the first side faces and the second side faces being orthogonal to the main surface.

13. The semiconductor device according to claim 12, wherein the recess is open to outside at the second side faces.

14. The semiconductor device according to claim 13, wherein the recess has a uniform cross section in the second direction.

15. The semiconductor device according to claim 1, wherein the substrate is made of a monocrystalline semiconductor material.

16. The semiconductor device according to claim 15, wherein the semiconductor material is Si.

17. The semiconductor device according to claim 16, wherein the main surface is a (100) surface.

18. The semiconductor device according to claim 1, further comprising an insulation layer formed over the main surface, the bottom surface and the sloped surfaces, wherein the conductive layer is in contact with the insulation layer.

19. The semiconductor device according to claim 18, wherein the insulation layer is made of SiO₂.

20. The semiconductor device according to claim 18, wherein the conductive layer further includes a barrier layer held in contact with the insulation layer.

21. The semiconductor device according to claim 20, wherein the barrier layer is made of Ti.

22. The semiconductor device according to claim 1, wherein the semiconductor element is a Hall-effect element.

23. A method of manufacturing a semiconductor device, the method comprising:

forming at least one groove in a semiconductor substrate having a main surface in a manner such that the groove recedes from the main surface and has a bottom surface and first and second sloped surfaces spaced apart from each other in a first direction perpendicular to a thickness direction of the substrate, and that the groove extends in a second direction perpendicular to both the thickness direction of the substrate and the first direction;

forming a conductive layer on the substrate including the groove;

mounting semiconductor elements on the bottom surface and with intervals between the semiconductor elements, the semiconductor elements being accommodated in the groove;

forming a sealing resin for covering the semiconductor elements; and

cutting the substrate along the first direction and the second direction thereby dividing the substrate into individual pieces each including one of the semiconductor elements,

wherein the forming of the conductive layer includes patterning by photolithography for forming the conductive layer on the substrate with the groove in a manner such that the photolithography forms first exposure regions at the first sloped surface and second exposure regions at the second sloped surface, and that none of the second exposure regions is line-symmetrical to any one of the first exposure regions with respect to an imaginary line parallel to the second direction.

24. The method according to claim 23, wherein the first exposure regions and the second exposure regions extend parallel to the first direction.

25. The method according to claim 24, wherein the patterning includes forming at least one bottom exposure region on the bottom surface, the bottom exposure region including an extension extending parallel to the second direction, and the bottom exposure region being connected to one of the first and the second exposure regions.

26. The method according to claim 25, wherein the extension of the bottom exposure region is in contact with an intersection between the bottom surface and one of the sloped surfaces.

27. The method according to claim 23, wherein the forming of the conductive layer includes forming a seed layer on the substrate with the groove before the patterning.

28. The method according to claim 27, wherein the seed layer is formed by sputtering.

29. The method according to claim 27, wherein the patterning includes removing a light-exposed portion of a resist layer on the substrate with a developing solution.

30. The method according to claim 29, wherein the forming of the conductive layer includes forming a plated layer on an exposed portion of the seed layer after the patterning.

31. The method according to claim 30, wherein the plated layer is formed by electrolytic plating.

32. The method according to claim 30, wherein the forming of the conductive layer includes removing a portion of the seed layer not covered with the plated layer after the forming of the plated layer.

33. The method according to claim 32, wherein the removing of the seed layer includes an etching process performed after the removing of the resist layer formed on the substrate with the grooves.

34. The method according to claim 27, further comprising forming an insulation layer on the substrate with the groove before the forming of the conductive layer.

35. The method according to claim 34, wherein the insulation layer is formed by thermal oxidation.

36. The method according to claim 34, wherein the forming of the conductive layer includes forming a barrier layer in contact with the insulation layer before the forming of the seed layer.

37. The method according to claim 36, wherein the barrier layer is formed by sputtering.

38. The method according to claim 23, wherein the substrate is made of a monocrystalline semiconductor material.

39. The method according to claim 38, wherein the semiconductor material is Si.

40. The method according to claim 39, wherein the main surface is a (100) surface.

41. The method according to claim 40, wherein the groove is formed by anisotropic etching with respect to the substrate.

42. The method according to claim 23, wherein the semiconductor elements are Hall-effect elements.