DISPLAY DEVICE

• US 20170059908A1
• Filed: 08/24/2016
• Published: 03/02/2017
• Est. Priority Date: 08/28/2015
• Status: Active Grant

• Current Assignee: InnoLux Corporation
• Original Assignee: InnoLux Corporation
• Inventors: YEN, Chung-Wen, LIU, Yu-Tsung, WANG, Chao-Hsiang, LEE, Te-Yu
• Granted Patent: US 10,670,935 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G02F 1/133345 Insulating layers G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence
• CPC Class Codes: G02F 1/13606 having means for reducing parasitic capacitance
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52

Abstract

The display device includes a first substrate; an active layer disposed on the first substrate; a first insulation layer disposed on the active layer; a first electrode layer disposed on the first insulation layer including a gate electrode line extending along a first direction and a protruding portion extending along a second direction; a second insulation layer disposed on the first electrode layer; and a second electrode layer disposed on the second insulation layer. The second electrode layer includes a date line extending along the second direction and a conductive layer. The conductive layer includes a first conductive portion and a second conductive portion, wherein the first conductive portion has a first maximum width A along the first direction, and the second conductive portion has a second maximum width B along the first direction. The first maximum width A is less than the second maximum width B.

Claims

1. A display device, comprising:

a first substrate;

a second substrate;

a display media layer disposed between the first substrate and the second substrate;

an active layer disposed on the first substrate;

a first insulation layer disposed on the active layer;

a first electrode layer disposed on the first insulation layer, wherein the first electrode layer includes a gate electrode line extending along a first direction, and a protruding portion extending along a second direction, wherein the first direction is orthogonal to the second direction;

a second insulation layer disposed on the first electrode layer; and

a second electrode layer disposed on the second insulation layer, wherein the second electrode layer includes a date line extending along the second direction and a conductive pattern, wherein the date line and the conductive pattern are in electrical contact with the active layer through the first contact via and the second contact via respectively, wherein the conductive pattern includes a first conductive portion and a second conductive portion and the first conductive portion connects the second conductive portion, wherein the first conductive portion has a first maximum width A along the first direction, and the second conductive portion has a second maximum width B along the first direction, and wherein the first maximum width A is less than the second maximum width B.

2. The display device as claimed in claim 1, wherein the gate electrode line is connected to the protruding portion.

3. The display device as claimed in claim 1, wherein the data line and a portion of the conductive pattern are disposed at two opposite sides of the protruding portion.

4. The display device as claimed in claim 1, wherein the first maximum width A is between 2.0 μ

m and 14.0 μ

m.

5. The display device as claimed in claim 1, wherein the second maximum width B is between 3.0 μ

m and 15.0.

6. The display device as claimed in claim 1, wherein the ratio of the first maximum width A to the second maximum width B is between 0.50 and 0.90.

7. The display device as claimed in claim 1, wherein the ratio of the first maximum width A to the second maximum width B is between 0.75 and 0.85.

8. A display device, comprising:

a first substrate;

a second substrate;

a display media layer disposed between the first substrate and the second substrate;

an active layer, disposed on the first substrate;

a first insulation layer disposed on the active layer;

a first electrode layer disposed on the first insulation layer, wherein the first electrode layer includes a gate electrode line extending along a first direction;

a second insulation disposed on the first electrode layer; and

a second electrode layer disposed on the second insulation layer, wherein the second electrode layer includes a data line extending along a second direction and a conductive pattern, wherein the first direction is orthogonal to the second direction, and the date line and the conductive pattern are in electrical contact with the active layer through the first contact via and the second contact via respectively,

wherein the gate electrode line includes a first gate electrode portion and a second gate electrode portion and the first gate electrode portion connects the second gate electrode portion, wherein the first gate electrode portion overlaps the active layer, wherein there is a first minimum distance D2 along the second direction between a projection of the first gate electrode portion onto the first substrate and a projection of the conductive pattern onto the first substrate, and there is a second minimum distance D3 along the second direction between a projection of the second gate electrode portion onto the first substrate and a projection of the conductive pattern onto the first substrate, wherein the first minimum distance D2 is greater than the second minimum distance D3.

9. The display device as claimed in claim 8, wherein the first minimum distance D2 is between 1.0 μ

m and 5.0 μ

m.

10. The display device as claimed in claim 8, wherein the first minimum distance D3 is between 0.5 μ

m and 4.5 μ

m.

11. The display device as claimed in claim 8, wherein the ratio of the minimum distance D3 to the minimum distance D2 is between 0.50 and 0.95.

12. The display device as claimed in claim 8, wherein the ratio of the minimum distance D3 to the minimum distance D2 is between 0.80 and 0.90.

13. The display device as claimed in claim 8, further comprising:

a third insulation layer disposed on the second electrode layer; and

a pixel electrode layer disposed on the third insulation layer, and connected to the conductive pattern via a third contact via, wherein a projection of the third contact via onto the first substrate has a first maximum width W1 in the first direction X and a second maximum width W2 in the first direction Y, and the first maximum width W1 is not equal to the second maximum width W2.

14. The display device as claimed in claim 13, wherein the first maximum width W1 is greater than the second maximum width W2, and the ratio of the second maximum width W2 to the first maximum width W1 is between 0.5 and 0.8.

15. The display device as claimed in claim 13, wherein the first maximum width W1 is less than the second maximum width W2, and the ratio of the first maximum width W1 to the second maximum width W2 is between 0.5 and 0.8.

16. A thin film transistor substrate, comprising:

a first substrate;

an active layer, disposed on the first substrate;

a first insulation layer disposed on the active layer;

a first electrode layer disposed on the first insulation layer, wherein the first electrode layer includes a gate electrode line extending along a first direction;

a second insulation layer disposed on the first electrode layer; and

a second electrode layer disposed on the second insulation layer, wherein the second electrode layer includes a data line extending along a second direction and a conductive pattern, wherein the first direction is orthogonal to the second direction, and the date line and the conductive pattern are in electrical contact with the active layer through the first contact via and the second contact via respectively,

wherein the gate electrode line includes a first gate electrode portion and a second gate electrode portion and the first gate electrode portion connects the second gate electrode portion, wherein the first gate electrode portion overlaps the active layer, wherein there is a first minimum distance D2 along the second direction between a projection of the first gate electrode portion onto the first substrate and a projection of the conductive pattern onto the first substrate, and there is a second minimum distance D3 along the second direction between a projection of the second gate electrode portion onto the first substrate and a projection of the conductive pattern onto the first substrate, wherein the first minimum distance D2 is greater than the second minimum distance D3.

17. The thin film transistor substrate as claimed in claim 16, wherein the first minimum distance D2 is between 1.0 μ

m and 5.0 μ

m.

18. The thin film transistor substrate as claimed in claim 16, wherein the first minimum distance D3 is between 0.5 μ

m and 4.5 μ

m.

19. The thin film transistor substrate as claimed in claim 16, wherein the ratio of the minimum distance D3 to the minimum distance D2 is between 0.50 and 0.95.

20. The thin film transistor substrate as claimed in claim 16, further comprising:

a third insulation layer disposed on the second electrode layer; and

a pixel electrode layer disposed on the third insulation layer, and connected to the conductive pattern via a third contact via, wherein a projection of the third contact via onto the first substrate has a first maximum width W1 in the and the first maximum width W1 is not equal to the second maximum width W2.