Out of Order Memory Command Fetching

• US 20170060422A1
• Filed: 10/30/2015
• Published: 03/02/2017
• Est. Priority Date: 08/31/2015
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Sharifie, Tal, Turjeman, Amir, Benisty, Shay
• Granted Patent: US 10,019,161 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 13/1673 using buffers
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 2213/0026 PCI express
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0629 Configuration or reconfiguration of storage systems
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A system and method that allows out of order fetching of host non-volatile memory commands can improve and maximize the memory device performance. The memory device can examine the non-volatile memory command headers available in the non-volatile memory command queue to select one or more, non-volatile memory commands to be fetched, in an optimum order and executed according to currently available resources in the memory device. The memory device can optimize performance of the non-volatile memory commands by re-ordering the host commands fetched from the host memory.

Claims

1. A memory system comprising:

a memory device coupled to a non-volatile memory command submission queue in a host computer system via a data communication bus, the non-volatile memory command submission queue including a plurality of non-volatile memory commands issued to the non-volatile memory command submission queue in a first order, the memory device including a plurality of memory dies, the plurality of memory dies including a corresponding plurality of non-volatile memory cells and a command fetching engine including;

an out of order selection module including;

logic operable to examine the plurality of non-volatile memory commands in the non-volatile memory command submission queue;

logic operable to identify an available memory resource in the memory device;

logic operable to identify a non-volatile memory command in the non-volatile memory command submission queue corresponding to the identified available memory resource in the memory device; and

logic operable to fetch the identified non-volatile memory command in a second order independent of the first order of the identified non-volatile memory command in the non-volatile memory command submission queue; and

the memory device including a memory controller including logic operable to process the fetched non-volatile memory commands in the second order.

2. The non-volatile memory system of claim 1, further comprising a read module, a write module and an admin module in the out of order selection module, wherein the read module, the write module and the admin module are coupled in parallel and are configured to operate simultaneously.

3. The non-volatile memory system of claim 2, wherein the read module includes:

logic operable to examine the plurality of non-volatile memory commands in the non-volatile memory command submission queue for a read memory command;

logic operable to identify an available read memory resource in the memory device;

logic operable to identify a read non-volatile memory command in the non-volatile memory command submission queue corresponding to the identified available read memory resource in the memory device; and

logic operable to fetch the identified read non-volatile memory command in a third order independent of the first order of the identified read non-volatile memory command in the non-volatile memory command submission queue.

4. The non-volatile memory system of claim 2, wherein the write module includes:

logic operable to examine the plurality of non-volatile memory commands in the non-volatile memory command submission queue for a write memory command;

logic operable to identify an available write memory resource in the memory device;

logic operable to identify a write non-volatile memory command in the non-volatile memory command submission queue corresponding to the identified available write memory resource in the memory device; and

logic operable to fetch the identified write non-volatile memory command in a fourth order independent of the first order of the identified write non-volatile memory command in the non-volatile memory command submission queue.

5. The non-volatile memory system of claim 2, wherein the admin module includes:

logic operable to examine the plurality of non-volatile memory commands non-volatile in the memory command submission queue for a admin memory command;

logic operable to identify an available admin memory resource in the memory device;

logic operable to identify a admin non-volatile memory command in the non-volatile memory command submission queue corresponding to the identified available admin memory resources in the memory device; and

logic operable to fetch the identified admin non-volatile memory command in a fifth order independent of the first order of the identified admin non-volatile memory command in the non-volatile memory command submission queue.

6. The non-volatile memory system of claim 1, further comprising logic operable to receive a notification from the host computer system that a new non-volatile memory command has been issued by the host computer system to the non-volatile memory command submission queue.

7. The non-volatile memory system of claim 1, further comprising logic operable to notify the host system that processing of a fetched non-volatile memory command has been completed when the fetched non-volatile memory command has been processed.

8. The non-volatile memory system of claim 1, further comprising logic operable to combine two or more fetched non-volatile memory commands to produce a combined non-volatile memory command and processing the combined non-volatile memory command as a single non-volatile memory command.

9. The non-volatile memory system of claim 8, wherein the two or more fetched non-volatile memory commands are read non-volatile memory commands.

10. The non-volatile memory system of claim 8, wherein the two or more fetched non-volatile memory commands are write non-volatile memory commands.

11. The non-volatile memory system of claim 8, wherein the two or more fetched non-volatile memory commands are admin non-volatile memory commands.

12. The non-volatile memory system of claim 8, wherein the two or more fetched non-volatile memory commands are non-volatile memory commands directed to a selected one memory die of the plurality of memory dies.

13. The non-volatile memory system of claim 1, wherein plurality of memory dies includes a plurality of planes of memory dies.

14. The non-volatile memory system of claim 1, wherein the logic operable to examine the plurality of memory commands in the non-volatile memory command submission queue includes logic operable to examine a plurality of fields included in each one of the plurality of non-volatile memory commands.

15. The non-volatile memory system of claim 14, wherein the plurality of fields included in each one of the plurality of non-volatile memory commands includes at least one of a group consisting of a command field, a data transfer type field, a fused operation field or an opcode field.

16. The non-volatile memory system of claim 1, wherein the logic operable to examine the plurality of non-volatile memory commands in the non-volatile memory command submission queue includes logic operable to examining a metadata for each one of the plurality of memory commands.

17. The non-volatile memory system of claim 1, wherein the data communication bus includes a PCI express data communication protocol.

18. A method of fetching memory commands from a plurality of memory command submission queues in a host computer system comprising:

receiving a notification in a memory device that a plurality of submission memory commands have been issued to the plurality of memory command submission queues in a first order;

examining the plurality of memory commands in the plurality of memory command submission queues;

identifying an available memory resource in the memory device;

identifying at least one memory command in the plurality of memory command submission queues corresponding to the identified available memory resource in the memory device;

fetching the at least one identified memory command in a second order independent of the first order of the identified at least one memory command in the plurality of memory command submission queues; and

processing the at least one fetched memory command in the second order.

19. The method of claim 18, wherein examining the plurality of memory commands in the plurality memory command submission queues, identifying the at least one memory command in the plurality memory command submission queues corresponding to the identified available memory resource in the memory device and fetching the identified at least one memory command in the second order independent of the first order of the identified at least one memory command in the memory command queue are conducted in parallel by a plurality of modules included in the memory device, wherein the plurality of modules include a read module, a write module and an admin module.

20. The method of claim 18, further comprising combining two or more fetched memory commands from one or more of the plurality memory command submission queues to produce a combined memory command and processing the combined memory command as a single memory command.