MEMORY ACTIVITY DRIVEN ADAPTIVE PERFORMANCE MEASUREMENT

• US 20170060476A1
• Filed: 08/31/2015
• Published: 03/02/2017
• Est. Priority Date: 08/31/2015
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Chinnakkonda Vidyapoornachary, Diyanesh B., Purushotham, Srinivas B.
• Granted Patent: US 10,067,672 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 1/20 Cooling means
• CPC Class Codes: G06F 1/206 comprising thermal management
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0634 by changing the state or mode of one or more devices
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 29/027 in fuses
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 5/143 Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels G11C5/148 takes precedence; Switching between alternative supplies G11C5/141 takes precedence
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 7/24 Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method of monitoring memory performance comprises selecting a first portion of memory from two or more portions of memory in accordance with an adaptive mode indicated by configuration bits in a control register; monitoring memory accesses to the selected portion of memory during a first sampling period; selecting a different portion of memory from the two or more portions of memory in accordance with the adaptive mode for monitoring the different portion of memory in a subsequent sampling period; monitoring memory accesses to the different portion of memory during the subsequent sampling period; recording a respective number of memory accesses for each portion of memory over a plurality of sampling periods; and generating one or more interrupts to output data regarding the monitored memory accesses for data analysis.

Claims

1-7. -7. (canceled)

8. A memory controller comprising:

a plurality of memory interfaces, each of the plurality of memory interfaces communicatively coupled to a respective memory module comprising at least one rank and at least one bank;

a profiler configured to maintain a record of respective memory accesses to each rank and to each bank of each memory module;

a control unit configured to adaptively select which portion of the respective memory modules coupled to the plurality of memory interfaces to monitor for each of a plurality of sampling periods based on one of a track hotness mode, a track coldness mode, and a round robin mode as indicated by bits in a control register; and

a counter configured to count the respective number of memory accesses to the selected portion of the memory modules during the respective sampling period;

wherein the control unit is further configured to generate interrupts periodically to provide data from the counter to a processor for data analysis.

9. The memory controller of claim 8, wherein the control unit is configured to adaptively select which portion of the respective memory modules to monitor based on the track hotness mode;

wherein the control unit is configured to retrieve data from the profiler regarding the number of memory accesses for each rank and to select the rank having the highest number of memory accesses for monitoring in the next sampling period.

10. The memory controller of claim 8, wherein the control unit is configured to adaptively select which portion of the respective memory modules to monitor based on the track coldness mode;

wherein the control unit is configured to retrieve data from the profiler regarding the number of memory accesses for each rank and to select the rank having the lowest number of memory accesses for monitoring in the next sampling period.

11. The memory controller of claim 8, wherein the control unit is configured to adaptively select which portion of the respective memory modules to monitor based on the round robin mode;

wherein the control unit is configured to rotate selection of each rank of the respective memory modules coupled to the plurality of memory interfaces such that each rank is monitored in a respective sampling period.

12. The memory controller of claim 11, wherein the memory controller further comprises a memory buffer;

wherein the control unit is configured to rotate selection of each rank of the respective memory modules coupled to the plurality of memory interfaces and the memory buffer such that each rank and memory buffer events are monitored in a respective sampling period.

13. The memory controller of claim 8, wherein the control unit is further configured to generate interrupts at predetermined time intervals.

14. The memory controller of claim 8, wherein the control unit is further configured to generate an interrupt when the counter has reached a predetermined limit.

15. A memory sub-system comprising:

a processor;

a plurality of memory modules each comprising at least one rank and at least one bank; and

a memory controller having a plurality of memory interfaces, each memory interface communicatively coupled to a respective one of the plurality of memory modules;

wherein the memory controller further comprises a performance measurement component configured to maintain a record of respective memory accesses to each rank and to each bank of each memory module and to adaptively select which portion of the respective memory modules to monitor for each of a plurality of sampling periods based on one of a track hotness mode, a track coldness mode, and a round robin mode as indicated by bits in a control register;

wherein the performance measurement component is further configured to count the respective number of memory accesses to the selected portion of the memory modules during the respective sampling period and to generate interrupts periodically to provide the counted number of memory accesses to the processor for data analysis.

16. The memory sub-system of claim 15, wherein the performance measurement component is configured to adaptively select which portion of the respective memory modules to monitor based on the track hotness mode;

wherein the performance measurement component is configured to select the rank having the highest number of memory accesses for monitoring in a next sampling period.

17. The memory sub-system of claim 15, wherein the performance measurement component is configured to adaptively select which portion of the respective memory modules to monitor based on the track coldness mode;

wherein the performance measurement component is configured to select the rank having the lowest number of memory accesses for monitoring in a next sampling period.

18. The memory sub-system of claim 15, wherein the performance measurement component is configured to adaptively select which portion of the respective memory modules to monitor based on the round robin mode;

wherein the performance measurement component is configured to rotate selection of each rank of the respective memory modules coupled to the plurality of memory interfaces such that each rank is monitored in a respective sampling period.

19. The memory sub-system of claim 18, wherein the memory controller further comprises a memory buffer;

wherein the performance measurement component is configured to rotate selection of each rank of the respective memory modules coupled to the plurality of memory interfaces and the memory buffer such that each rank and memory buffer events are monitored in a respective sampling period.

20. The memory sub-system of claim 15, wherein the performance measurement unit is further configured to generate interrupts at predetermined time intervals.