ELECTRONIC DEVICE AND DATA EXCHANGE METHOD INCLUDING PROTOCOL INDICATIVE OF MODES OF OPERATION

• US 20170060785A1
• Filed: 04/20/2016
• Published: 03/02/2017
• Est. Priority Date: 08/31/2015
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: CHANG, Kuen Long, WANG, Yu Chen, CHEN, Ken Hui
• Granted Patent: US 10,409,735 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 13/126 and has means for transferring I/O instructions and statuses between control unit and main processor
• CPC Class Codes: G06F 13/364 using independent requests or grants, e.g. using separated request and grant lines
• CPC Class Codes: G06F 13/404 with address mapping
• CPC Class Codes: G06F 13/4291 using a clocked protocol

Abstract

An electronic device includes a processor coupled to a memory device, through a data bus to receive and transmit bits on the data bus. The processor is configured to transmit a message including a first bit indicative of controlling the data bus, address bits indicative of an address identifying the memory device, and a second bit indicative of whether the processor intends to read data from or write data to the memory device; and transmit a third bit indicative of a mode of operation of the memory device,

Claims

1. An electronic device, comprising:

a processor coupled to a memory device, through a data bus to receive and transmit bits on the data bus, the processor being configured to;

transmit a message including a first bit indicative of controlling the data bus, address bits indicative of an address identifying the memory device, and a second bit indicative of whether the processor intends to read data from or write data to the memory device; and

transmit a third bit indicative of a mode of operation of the memory device.

2. The electronic device according to claim 1, wherein the processor is further configured to transmit a fourth bit indicative of concluding communication with the memory device or retaining control of the data bus.

3. The electronic device according to claim 1, the processor is further configured to transmit bits of data or memory address information, wherein the third bit is transmitted between the second bit and the bits of data or memory address information.

4. The electronic device according to claim 1, the processor is further configured to transmit bits of data or memory address information, wherein the third bit is transmitted after the bits of data or memory address information.

5. The electronic device according to claim 2, wherein the third bit is transmitted before the fourth bit.

6. The electronic device according to claim 1, wherein the processor is further configured to:

transmit bits of data or memory address information;

receive a first acknowledgement from the memory device between transmitting the message and transmitting the third bit; and

receive a second acknowledgement from the memory device between transmitting the third bit and transmitting the bits of data or memory address information.

7. The electronic device according to claim 1, wherein the mode of operation is selected from one of erasing data from the memory device, programming the memory device, or reading data from the memory device at a predetermined speed.

8. A memory device coupled to a control unit, through a data bus to receive and transmit bits on the data bus, the memory device being configured to:

receive a message from the control unit, the message including a first bit indicative of the control unit controlling the data bus, address bits indicative of an address identifying the memory device, and a second bit indicative of whether the control unit intends to read data from or write data to the memory device; and

receive a third bit from the control unit, the third bit being indicative of a mode of operation of the memory device.

9. The memory device according to claim 8, wherein the memory device is further configured to:

in response to the receipt of he message, transmit a first acknowledgement to the control unit; and

in response to the receipt of the third bit, transmit a second acknowledgement to the control unit.

10. The memory device according to claim 8, wherein in response to the third bit, the memory device is configured to perform one of erasing data from the memory device, programming the memory device, or reading data from the memory device at a predetermined speed.

11. The memory device according to claim 8, wherein the memory device is a flash memory device,

12. A data exchange method executable by an electronic device, the electronic device including a data bus, and a processor coupled to a memory device through the data bus to receive and transmit bits on the data bus, the method comprising:

transmitting, by the processor, a message including a first bit indicative of controlling the data bus, address bits indicative of an address identifying the memory device, and a second bit indicative of whether the processor intends to read data from or write data to the memory device; and

transmitting, by the processor, a third bit indicative of a mode of operation of the memory device.

13. The method according to claim 12, further comprising transmitting, by the processor, a fourth bit indicative of concluding communication with the memory device or retaining control of the data bus.

14. The method according to claim 12, further comprising:

transmitting bits of data or memory address information,

wherein the third bit is transmitted between the second bit and the data or memory address information.

15. The method according to claim 12,

transmitting bits of data or memory address information,

wherein the third bit is transmitted after the data or memory address information.

16. The method according to claim 13, wherein the third bit is transmitted before the fourth bit.

17. The method according to claim 12, further comprising:

transmitting bits of data or memory address information,

receiving a first acknowledgement between transmitting the message and transmitting the third bit; and

receiving a second acknowledgement between transmitting the third bit and transmitting the data or memory address information.

18. The method according to claim 12, wherein the mode of operation is selected from one of erasing data from the memory device, programming the memory device, or reading data from the memory device at a predetermined speed.

19. A data exchange method executable by a memory device coupled to a control unit through a data bus to receive and transmit bits on the data bus, the method comprising:

receiving a message from the control unit, the message including a first bit indicative of controlling the data bus, address bits indicative of an address identifying the memory device, and a second bit indicative of whether the control unit intends to read data from or write data to the memory device; and

receiving a third bit from the control unit indicative of a mode of operation of the memory device; and

20. The data exchange method according to claim 19, further comprising:

in response to the third bit, performing one of erasing data from the memory device, programming the memory device, or reading data from the memory device in a predetermined speed.