MEMORY SYSTEM INCLUDING PLURAL MEMORY DEVICES FORMING PLURAL RANKS AND MEMORY CONTROLLER ACCESSING PLURAL MEMORY RANKS AND METHOD OF OPERATING THE MEMORY SYSTEM
First Claim
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1. A memory system comprising:
- a plurality of memory devices included in a plurality of memory groups; and
a memory controller configured to independently access the memory groups,wherein the memory controller is configured to allocate allocation units having different sizes to different memory groups and perform a write operation based on an allocation unit of one of the memory groups.
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Abstract
The inventive concept relates to a memory system. The memory system of the inventive concept includes a plurality of memory devices included in a plurality of memory groups, and a memory controller configured to independently access the memory groups. The memory controller is configured to allocate allocation units having different sizes to different memory groups and perform a write operation based on an allocation unit of one of the memory groups.
14 Citations
20 Claims
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1. A memory system comprising:
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a plurality of memory devices included in a plurality of memory groups; and a memory controller configured to independently access the memory groups, wherein the memory controller is configured to allocate allocation units having different sizes to different memory groups and perform a write operation based on an allocation unit of one of the memory groups. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A method of operating a memory system, the memory system comprising a plurality of memory devices, included in a first memory group and a second memory group, and a memory controller, the method comprising:
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receiving, by the memory controller, a write request; writing, by the memory controller, write data to the first memory group in response to a size of the write data associated with the write request being equal to or smaller than a reference size; and writing, by the memory controller, the write data to the second memory group in response to the size of write data associated with the write request being greater than the reference size, wherein the first memory group and the second memory group enter a sleep mode independently of each other. - View Dependent Claims (14, 15)
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16. A memory controller comprising:
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an interface configured to connect to a plurality of memory devices; and a memory allocator, implemented by at least one hardware processor, configured to manage storage spaces of the plurality of memory devices according to ranks, wherein a rank to which write data is to be stored is determined according to a size of the write data, and each rank is accessed by the memory controller independently of each other. - View Dependent Claims (17, 18, 19, 20)
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Specification