SEMICONDUCTOR MEMORY DEVICE

• US 20170062033A1
• Filed: 03/09/2016
• Published: 03/02/2017
• Est. Priority Date: 08/25/2015
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: FUJITA, Katsuyuki
• Granted Patent: US 9,747,966 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1697 Power supply circuits
• CPC Class Codes: G11C 2207/002 Isolation gates, i.e. gates coupling bit lines to the sense amplifier
• CPC Class Codes: G11C 5/146 Substrate bias generators G11C5/141 takes precedence
• CPC Class Codes: H10B 61/20 comprising components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10N 50/10 Magnetoresistive devices

Abstract

According to one embodiment, a semiconductor memory device includes a memory cell; a reference signal generation circuit; a sense amplifier; a first transistor configured to electrically couple the memory cell and a first input terminal of the sense amplifier; a second transistor configured to electrically couple the reference signal generation circuit and a second input terminal of the sense amplifier; a first control circuit configured to supply a voltage to gates of the first transistor and the second transistor; a second control circuit configured to supply a first voltage except 0V to a back gate of the first transistor; and a third control circuit configured to supply a second voltage except 0V to a back gate of the second transistor.

Claims

1. A semiconductor memory device comprising:

a memory cell which includes a variable resistance element;

a reference signal generation circuit configured to generate a reference signal;

a sense amplifier including a first input terminal and a second input terminal;

a first transistor configured to electrically couple the memory cell and the first input terminal of the sense amplifier;

a second transistor configured to electrically couple the reference signal generation circuit and the second input terminal of the sense amplifier;

a first control circuit configured to supply a voltage to gates of the first transistor and the second transistor;

a second control circuit configured to supply a first voltage except 0V to a back gate of the first transistor; and

a third control circuit configured to supply a second voltage except 0V to a back gate of the second transistor.

2. The device of claim 1, wherein the second control circuit configured to supply the first voltage having temperature dependency and/or the third control circuit configured to supply the second voltage having temperature dependency.

3. The device of claim 1, wherein the second control circuit configured to supply the first voltage being negative voltage and/or the third control circuit configured to supply the second voltage being negative voltage.

4. The device of claim 1, wherein during a read operation, the second control circuit supplies the first voltage and/or the third control circuit supplies the second voltage.

5. The device of claim 1, wherein

the first transistor and the second transistor have positive threshold voltages, and

during a read operation, the first control circuit supplies a power supply voltage to the gates of the first transistor and the second transistor.

6. The device of claim 1, wherein

the second control circuit comprises:

a first operational amplifier configured to compare a third voltage which has temperature dependency and a fourth voltage based on the first voltage, and configured to output a fifth voltage based on a result of the comparison; and

a first negative voltage generation pump configured to operate in accordance with the fifth voltage.

7. The device of claim 6, wherein

the second control circuit further comprises:

a third operational amplifier configured to compare the third voltage and a sixth voltage based on the first voltage, and configured to output a seventh voltage based on a result of the comparison; and

a fourth transistor having a gate supplied with the seventh voltage.

8. The device of claim 1, wherein

the third control circuit comprises:

a second operational amplifier configured to compare an eighth voltage which has temperature dependency and a ninth voltage based on the second voltage, and configured to output a tenth voltage based on a result of the comparison; and

a second negative voltage generation pump configured to operate in accordance with the tenth voltage.

9. The device of claim 8, wherein

the third control circuit further comprises:

a fourth operational amplifier configured to compare the eighth voltage and a eleventh voltage based on the first voltage, and to output a twelfth voltage based on a result of the comparison; and

a fifth transistor having a gate supplied with the twelfth voltage.

10. The device of claim 1, further comprising a functional circuit including a third transistor,

wherein the threshold voltages of the first transistor and the second transistor are greater than a threshold voltage of the third transistor.

11. The device of claim 1, wherein

the first transistor and the second transistor have negative threshold voltages, and

during a read operation, the first control circuit supplies a ground voltage to the gates of the first transistor and the second transistor.

15. The device of claim 1, further comprising a second transistor configured to electrically couple the memory cell and the second input terminal of the sense amplifier,

wherein in a read operation, a fixed voltage is supplied to a back gate of the second transistor.

12. A semiconductor memory device comprising:

a memory cell which includes a variable resistance element;

a reference signal generation circuit configured to generate a reference signal;

a sense amplifier including a first input terminal and a second input terminal;

a first transistor configured to electrically couple the reference signal generation circuit and the first input terminal of the sense amplifier;

a first control circuit configured to supply a voltage to gates of the first transistor; and

a second control circuit configured to supply a first voltage except 0V to a back gate of the first transistor.

13. The device of claim 12, wherein the second control circuit configured to supply the first voltage having temperature dependency.

14. The device of claim 12, wherein

the first transistor has positive threshold voltage, and

during a read operation, the first control circuit supplies a power supply voltage to the gates of the first transistor.

16. A semiconductor memory device comprising:

a memory cell which includes a variable resistance element;

a sense amplifier including a first input terminal and a second input terminal;

a first transistor configured to electrically couple the memory cell and the first input terminal of the sense amplifier;

a first control circuit configured to supply a voltage to gates of the first transistor; and

a second control circuit configured to supply a first voltage except 0V to a back gate of the first transistor.

17. The device of claim 16, wherein the second control circuit configured to supply the first voltage having temperature dependency.

18. The device of claim 16, wherein

the first transistor has positive threshold voltage, and

during a read operation, the first control circuit supplies a power supply voltage to the gates of the first transistor.

19. The device of claim 16, further comprising:

a reference signal generation circuit configured to generate a reference signal; and

a second transistor configured to electrically couple the memory cell and the second input terminal of the sense amplifier,

wherein in a read operation, a fixed voltage is supplied to a back gate of the second transistor.

20. A semiconductor memory device comprising:

a memory cell which includes a variable resistance element;

a reference signal generation circuit configured to generate a reference signal;

a sense amplifier including a first input terminal and a second input terminal;

a first transistor configured to electrically couple the memory cell and the first input terminal of the sense amplifier; and

a second transistor configured to electrically couple the reference signal generation circuit and the second input terminal of the sense amplifier,

wherein a back gate of the first transistor is electrically isolated from a back gate of the second transistor.

21. A semiconductor memory device comprising:

a memory cell which includes a variable resistance element;

a reference signal generation circuit configured to generate a reference signal;

a sense amplifier including a first input terminal and a second input terminal;

a first transistor configured to electrically couple the memory cell and the first input terminal of the sense amplifier;

a second transistor configured to electrically couple the reference signal generation circuit and the second input terminal of the sense amplifier; and

a first control circuit configured to supply a voltage to gates of the first transistor and the second transistor,

wherein a first voltage except 0V is supplied to a back gate of the first transistor and a second voltage except 0V is supplied to a back gate of the second transistor.