SENSE AMPLIFIER WITH OFFSET COMPENSATION

• US 20170062036A1
• Filed: 08/25/2015
• Published: 03/02/2017
• Est. Priority Date: 08/25/2015
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: GLAZEWSKI, ROBERT ANTONI, HEINRICH-BARNA, STEPHEN KEITH, QIDWAI, SAIM AHMAD
• Granted Patent: US 9,704,554 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/221 using ferroelectric capacitors
• CPC Class Codes: G11C 11/223 using MOS with ferroelectric gate insulating film
• CPC Class Codes: G11C 11/2273 Reading or sensing circuits or methods
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: H03F 1/0205 in transistor amplifiers
• CPC Class Codes: H03F 3/16 with field-effect devices

Abstract

An amplifier circuit is disclosed having an amplifier with first and second input terminals coupled to receive an input signal. A first compensation circuit is coupled to the first input terminal, and a second compensation circuit is coupled to the second input terminal. A programmable latch circuit is arranged to select one of the first and second compensation circuits.

Claims

1. An amplifier circuit, comprising:

an amplifier having first and second input terminals;

a first compensation circuit coupled to the first input terminal;

a second compensation circuit coupled to the second input terminal; and

a programmable latch circuit arranged to select only one of the first and second compensation circuits.

2. The amplifier circuit of claim 1, wherein the first compensation circuit comprises a first capacitor connected in series with a first transistor, and wherein the second compensation circuit comprises a second capacitor connected in series with a second transistor.

3. The amplifier circuit of claim 1, wherein the first compensation circuit comprises a plurality of capacitors having a substantially same value, and wherein the second compensation circuit comprises a plurality of capacitors having the substantially same value.

4. The amplifier circuit of claim 1, wherein the first compensation circuit comprises a plurality of capacitors having binary weighted values, and wherein the second compensation circuit comprises a plurality of capacitors having the binary weighted values.

5. The amplifier circuit of claim 1, wherein the programmable latch circuit comprises a plurality of electronic fuse latch circuits.

6. The amplifier circuit of claim 1, wherein the programmable latch circuit comprises a plurality of electronic antifuse latch circuits.

7. The amplifier circuit of claim 1, wherein the programmable latch circuit comprises a plurality of latch circuits coupled to receive data from a nonvolatile memory array.

8. The amplifier circuit of claim 1, comprising a sense amplifier circuit of a memory array.

9. The amplifier circuit of claim 1, comprising a column of memory cells having a normal array of memory cells and a reserved array of memory cells.

10-15. -15. (canceled)

16. A system, comprising:

a processor circuit;

an input device coupled to the processor circuit;

an output device coupled to the processor circuit;

a memory array coupled to the processor circuit; and

a sense amplifier of the memory array, comprising;

a first compensation circuit coupled to a first input terminal of the sense amplifier;

a second compensation circuit coupled to a second input terminal of the sense amplifier; and

a programmable latch circuit arranged to select only one of the first and second compensation circuits.

17. The system of claim 16, wherein the first compensation circuit comprises a first capacitor connected in series with a first transistor, and wherein the second compensation circuit comprises a second capacitor connected in series with a second transistor.

18. The system of claim 16, wherein the programmable latch circuit comprises a plurality of electronic fuse latch circuits.

19. The system of claim 16, wherein the programmable latch circuit comprises a plurality of latch circuits coupled to receive data from a nonvolatile memory array.

20. The system of claim 16, comprising a column of memory cells having a normal array of memory cells and a reserved array of memory cells coupled to the sense amplifier.

21. A circuit, comprising:

a memory array having a plurality of memory cells connected to first and second bit lines;

a sense amplifier having a first input terminal coupled to the first bit line and having a second input terminal coupled to the second bit line;

a first compensation circuit coupled to the first input terminal;

a second compensation circuit coupled to the second input terminal; and

a programmable latch circuit arranged to select only one of the first and second compensation circuits.

22. The circuit of claim 21, wherein the first compensation circuit comprises a first capacitor connected in series with a first transistor, and wherein the second compensation circuit comprises a second capacitor connected in series with a second transistor.

23. The circuit of claim 21, wherein the first compensation circuit comprises a plurality of capacitors having a substantially same value, and wherein the second compensation circuit comprises a plurality of capacitors having the substantially same value.

24. The circuit of claim 21, wherein the first compensation circuit comprises a plurality of capacitors having binary weighted values, and wherein the second compensation circuit comprises a plurality of capacitors having the binary weighted values.

25. The circuit of claim 21, wherein the programmable latch circuit comprises a plurality of electronic fuse latch circuits.

26. The circuit of claim 21, wherein the programmable latch circuit comprises a plurality of latch circuits coupled to receive data from a nonvolatile memory array.