INTEGRATED CIRCUIT WITH ELECTRICAL FUSE AND METHOD OF FORMING THE SAME
First Claim
1. A method of forming an integrated circuit, the method comprising:
- forming at least one transistor over a substrate, wherein forming the at least one transistor comprises;
forming a gate dielectric structure over a substrate;
forming a work-function metallic layer over the gate dielectric structure;
forming a conductive layer over the work-function metallic layer; and
forming a source/drain (S/D) region being disposed adjacent to each sidewall of the gate dielectric structure;
forming a diffusion barrier layer between the gate dielectric structure and the work-function layer; and
forming at least one electrical fuse over the substrate, wherein forming the at least one electrical fuse comprises;
forming a first semiconductor layer over the substrate; and
forming a first silicide layer on the first semiconductor layer, wherein the diffusion barrier layer is formed before the first silicide layer.
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Accused Products
Abstract
A method of forming an integrated circuit. The method includes forming at least one transistor and at least one electrical fuse over a substrate. Forming the at least one transistor includes forming a gate dielectric structure over a substrate and a work-function metallic layer over the gate dielectric structure. Forming the at least one transistor further includes forming a conductive layer over the work-function metallic layer and a source/drain (S/D) region being disposed adjacent to each sidewall of the gate dielectric structure. Forming the at least one transistor further includes forming a diffusion barrier layer between the gate dielectric structure and the work-function layer. Forming the at least one electrical fuse includes forming a first semiconductor layer over the substrate. Forming the at least one electrical fuse includes forming a first silicide layer on the first semiconductor layer, wherein the diffusion barrier layer is formed before the first silicide layer.
11 Citations
20 Claims
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1. A method of forming an integrated circuit, the method comprising:
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forming at least one transistor over a substrate, wherein forming the at least one transistor comprises; forming a gate dielectric structure over a substrate; forming a work-function metallic layer over the gate dielectric structure; forming a conductive layer over the work-function metallic layer; and forming a source/drain (S/D) region being disposed adjacent to each sidewall of the gate dielectric structure; forming a diffusion barrier layer between the gate dielectric structure and the work-function layer; and forming at least one electrical fuse over the substrate, wherein forming the at least one electrical fuse comprises; forming a first semiconductor layer over the substrate; and forming a first silicide layer on the first semiconductor layer, wherein the diffusion barrier layer is formed before the first silicide layer. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method of forming an integrated circuit, the method comprising:
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forming a first semiconductor layer in a transistor region over a substrate and a second semiconductor layer in a fuse region over the substrate; forming a first silicide layer on the first semiconductor layer and a second silicide layer on the second semiconductor layer; forming a dielectric layer around the first and second semiconductor layers, exposing the first and second silicide layers; forming a cap layer covering the second silicide layer and exposing the first silicide layer; removing the first silicide layer and the first semiconductor layer to form a first opening that is left by the removed first silicide layer and the removed first semiconductor layer; sequentially forming a work-function metallic layer and a conductive layer in the first opening; and forming a diffusion barrier between the substrate and the work-function metallic layer, wherein the diffusion barrier is formed before the first silicide layer. - View Dependent Claims (9, 10)
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11. An integrated circuit comprising:
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at least one transistor and at least one electrical fuse disposed over the substrate, wherein the at least one transistor comprises; a gate dielectric structure over the substrate; a work-function layer over the gate dielectric structure; a conductive layer over the work-function metallic layer; and a source/drain (S/D) region adjacent to each sidewall of the gate dielectric structure; a diffusion barrier between the gate dielectric structure and the work-function layer; and wherein the at least one electrical fuse comprises; a first semiconductor layer over the substrate; and a first silicide layer on the first semiconductor layer. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification