METHODS OF FORMING SEMICONDUCTOR DEVICE STRUCTURES INCLUDING STAIR STEP STRUCTURES, AND RELATED SEMICONDUCTOR DEVICE STRUCTURES AND SEMICONDUCTOR DEVICES
First Claim
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1. A method of forming a semiconductor device structure, comprising:
- forming tiers comprising conductive structures and insulating structures in a stacked arrangement over a substrate;
selectively removing portions of the tiers to form a stair step structure comprising a selected number of steps, and forming at least some of the steps of the stair step structure to exhibit relatively larger widths than at least some other of the steps of the stair step structure based on increases in mathematically modeled error associated with laterally sizing and positioning steps of another stair case structure having the same number of steps and overall width as the stair step structure to receive structures thereon; and
forming contact structures on the steps of the stair step structure.
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Abstract
A method of forming a semiconductor device assembly comprises forming tiers comprising conductive structures and insulating structures in a stacked arrangement over a substrate. Portions of the tiers are selectively removed to form a stair step structure comprising a selected number of steps exhibiting different widths corresponding to variances in projected error associated with forming the steps. Contact structures are formed on the steps of the stair step structure. Semiconductor device structures and semiconductor devices are also described.
19 Citations
26 Claims
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1. A method of forming a semiconductor device structure, comprising:
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forming tiers comprising conductive structures and insulating structures in a stacked arrangement over a substrate; selectively removing portions of the tiers to form a stair step structure comprising a selected number of steps, and forming at least some of the steps of the stair step structure to exhibit relatively larger widths than at least some other of the steps of the stair step structure based on increases in mathematically modeled error associated with laterally sizing and positioning steps of another stair case structure having the same number of steps and overall width as the stair step structure to receive structures thereon; and forming contact structures on the steps of the stair step structure. - View Dependent Claims (2, 3, 5, 6, 7, 8, 9, 10, 21, 22, 23, 24, 25)
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4. (canceled)
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11-20. -20. (canceled)
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26. A method of forming a semiconductor device structure, comprising:
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forming a stack structure comprising conductive tiers over a substrate, each of the conductive tiers comprising a conductive structure and an insulating structure longitudinally adjacent the conductive structure; generating a mathematically modeled error distribution associated with forming a theoretical stair case structure exhibiting predetermined step widths and lateral positions from the stack structure using a mathematical modeling process; subjecting the stack structure to multiple material removal processes to remove portions of the tiers thereof and form an actual stair step structure comprising steps exhibiting different widths than one another, at least some of the steps of the actual stair step structure formed to exhibit relatively increased widths based on relatively increased mathematically modeled error values of the mathematically modeled error distribution associated with forming longitudinally corresponding steps of the theoretical stair case structure; and forming non-uniformly laterally spaced contact structures on the steps of the actual stair step structure.
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Specification