SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME

• US 20170062362A1
• Filed: 08/09/2016
• Published: 03/02/2017
• Est. Priority Date: 08/26/2015
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: SEKIKAWA, Hiroaki
• Granted Patent: US 9,679,858 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/76852 the layer also covering the sidewalls of the conductive structure
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 2224/0218 Structure of the auxiliary member
• CPC Class Codes: H01L 2224/0219 Material of the auxiliary member
• CPC Class Codes: H01L 2224/02315 Self-assembly processes
• CPC Class Codes: H01L 2224/02317 by local deposition
• CPC Class Codes: H01L 2224/02331 Multilayer structure
• CPC Class Codes: H01L 2224/0235 Shape of the redistribution layers
• CPC Class Codes: H01L 2224/0236 Shape of the insulating layers therebetween
• CPC Class Codes: H01L 2224/02371 connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/02373 Layout of the redistribution layers
• CPC Class Codes: H01L 2224/02379 Fan-out arrangement
• CPC Class Codes: H01L 2224/0239 Material of the redistribution layers
• CPC Class Codes: H01L 2224/024 Material of the insulating layers therebetween
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05007 comprising a core and a coating
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05166 : Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05548 : Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05664 : Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/4502 : Disposition
• CPC Class Codes: H01L 2224/45144 : Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 : Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48463 : the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 23/293 : Organic, e.g. plastic
• CPC Class Codes: H01L 23/3192 : Multilayer coating
• CPC Class Codes: H01L 23/522 : including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5228 : Resistive arrangements or effects of, or between, wiring layers other resistive arrangements H01L23/647
• CPC Class Codes: H01L 23/525 : with adaptable interconnections
• CPC Class Codes: H01L 23/528 : Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/5283 : Cross-sectional geometry
• CPC Class Codes: H01L 23/53238 : Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 24/02 : Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/85 : using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/00015 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/013 : Alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/07025 : Polyimide
• CPC Class Codes: H01L 2924/3511 : Warping
• CPC Class Codes: H01L 2924/35121 : Peeling or delaminating

Abstract

To provide a semiconductor device having improved reliability. The semiconductor device is equipped with a first polyimide film, rewirings formed over the first polyimide film, first and second dummy patterns formed over the first polyimide film, a second polyimide film that covers the rewirings and the dummy patterns, and an opening portion that exposes a portion of the rewirings in the second polyimide film. The first dummy pattern is, in plan view, comprised of a closed pattern surrounding the rewirings while having a space therebetween.

Claims

1. A semiconductor device, comprising

a first polyimide film;

a wiring formed over the first polyimide film;

a conductor pattern formed over the first polyimide film;

a second polyimide film that covers the wiring and the conductor pattern; and

an opening portion that exposes a portion of the wiring in the second polyimide film,

wherein, in plan view, the conductor pattern is comprised of a closed pattern surrounding the wiring, while having a space therebetween.

2. The semiconductor device according to claim 1,

wherein the wiring and the conductor pattern are placed each other separately with a predetermined distance.

3. The semiconductor device according to claim 1,

wherein the wiring comprises:

a barrier conductor film;

a first conductor film formed over the barrier conductor film; and

a second conductor film formed over the first conductor film.

4. The semiconductor device according to claim 3,

wherein the second conductor film is formed over the top surface and the side surface of the wiring.

5. The semiconductor device according to claim 4,

wherein the first conductor film is comprised of a copper film, and

wherein the second conductor film is comprised of a titanium film and a palladium film formed over the titanium film.

6. The semiconductor device according to claim 5,

wherein a copper wire is coupled to the second conductor film exposed from the opening portion.

7. The semiconductor device according to claim 1,

wherein the conductor pattern has a floating potential.

8. The semiconductor device according to claim 1,

wherein the first polyimide film has thereover an occupancy control pattern.

9. A semiconductor device, comprising:

a first polyimide film;

a plurality of wirings formed over the first polyimide film;

a plurality of conductor patterns formed over the first polyimide film;

a second polyimide film that covers the wirings and the conductor patterns; and

an opening portion that exposes a portion of each of the wirings in the second polyimide film,

wherein, in plan view, a first conductor pattern, among the conductor patterns, is comprised of a closed pattern surrounding a first wiring group, among the wirings, while having a space therebetween.

10. The semiconductor device according to claim 9,

wherein, in plan view, a second conductor pattern, among the conductor patterns, is comprised of a closed pattern surrounding a second wiring, among the wirings, while having therebetween a space.

11. The semiconductor device according to claim 10,

wherein the first conductor pattern and the second conductor pattern are coupled to each other, and

wherein a width of a coupled portion of the first conductor pattern and the second conductor pattern is greater than a width of the first conductor pattern and a width of the second conductor pattern.

12. The semiconductor device according to claim 9,

wherein a third conductor pattern, among the conductor patterns, is comprised of a closed pattern surrounding the first conductor pattern while having a space therebetween.

13. A method of manufacturing a semiconductor device, comprising the steps of:

(a) forming an insulating film that covers a pad;

(b) forming, in the insulating film, a first opening portion exposing a portion of a surface of the pad;

(c) forming a first polyimide film over the insulating film;

(d) forming, in the first polyimide film, a second opening portion to couple with the first opening portion;

(e) forming a wiring that fills the first opening portion and the second opening portion and is allocated over the first polyimide film, and a conductor pattern that be allocated over the first polyimide film;

(f) forming a second polyimide film that covers the wiring and the conductor pattern; and

(g) forming, in the second polyimide film, a third opening portion that exposes a portion of the wiring,

wherein in the step (e), the conductor pattern is comprised of a closed pattern that surrounds, in plan view, the wiring, while having a space therebetween.

14. The method of manufacturing a semiconductor device according to claim 13,

wherein the step (e) comprises the steps of:

(e1) forming a barrier conductor film over the first polyimide film including an inner wall of the first opening portion and an inner wall of the second opening portion;

(e2) forming a seed film over the barrier conductor film;

(e3) forming a first resist film over the seed film;

(e4) forming, in the first resist film, an opening portion for forming a wiring and an opening portion for forming a conductor pattern;

(e5) forming a first conductor film in the opening portion for forming the wiring and the opening portion for forming the conductor pattern;

(e6) after the step (e5), removing the first resist film and removing the seed film exposed by removing the first resist film;

(e7) after the step (e6), forming a second conductor film over barrier conductor film including the top surface and side surface of the first conductor film;

(e8) forming a second resist film over the second conductor film;

(e9) patterning the second resist film; and

(e10) removing the exposed second conductor film with the patterned second resist film as a mask.

15. The method of manufacturing a semiconductor device according to claim 14,

wherein the step (e4) further comprises the steps of:

(e41) patterning the first resist film; and

(e42) after the step (e41), curing the patterned first resist film.

16. The method of manufacturing a semiconductor device according to claim 14,

wherein in the step (e7), forming the second conductor film by sputtering.

17. The method of manufacturing a semiconductor device according to claim 16,

wherein the second conductor film has a titanium film and a palladium film.

18. The method of manufacturing a semiconductor device according to claim 14,

wherein in the step (e10), the exposed second conductor film is removed by wet etching.