Semiconductor Device and Method of Forming Interconnect Structure and Mounting Semiconductor Die in Recessed Encapsulant

• US 20170062390A1
• Filed: 11/11/2016
• Published: 03/02/2017
• Est. Priority Date: 05/14/2010
• Status: Abandoned Application

• Current Assignee: Stats Chippac Pte. Ltd. (JCET Group Co., Ltd.)
• Original Assignee: Stats Chippac Pte. Ltd. (JCET Group Co., Ltd.)
• Inventors: Chua, Linda Pei Ee, Do, Byung Tai, Pagaila, Reza A.
• Application Number:
  US15/349,838
• Publication Number:
  US 20170062390A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/288 from a liquid, e.g. electrolytic deposition
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13113 Bismuth [Bi] as principal constituent
• CPC Class Codes: H01L 2224/13116 Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/13124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/13139 : Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13144 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/16145 : the bodies being stacked
• CPC Class Codes: H01L 2224/16225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 : the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 2224/2518 : being disposed on at least two different sides of the body, e.g. dual array
• CPC Class Codes: H01L 2224/2919 : with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32145 : the bodies being stacked
• CPC Class Codes: H01L 2224/32502 : comprising an eutectic alloy
• CPC Class Codes: H01L 2224/48091 : Arched
• CPC Class Codes: H01L 2224/48106 : the connector being orthogonal to a side surface of the semiconductor or solid-state body, e.g. parallel layout
• CPC Class Codes: H01L 2224/48228 : the bond pad being disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/73253 : Bump and layer connectors
• CPC Class Codes: H01L 2224/73259 : Bump and HDI connectors
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/81 : using a bump connector
• CPC Class Codes: H01L 2224/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/0651 : Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06548 : Conductive via connections through the substrate, container, or encapsulation
• CPC Class Codes: H01L 2225/1035 : the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1041 : Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 2225/1088 : Arrangements to limit the height of the assembly
• CPC Class Codes: H01L 23/13 : characterised by the shape
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/48 : Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49811 : Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49838 : Geometry or layout
• CPC Class Codes: H01L 23/52 : Arrangements for conducting electric current within the device in operation from one component to another , i.e. interconnections, e.g. wires, lead frames optical interconnections G02B6/00
• CPC Class Codes: H01L 23/5384 : Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 23/552 : Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/03 : all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 29/40 : Electrodes ; Multistep manufacturing processes therefor
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/1815 : Shape

Abstract

A semiconductor device has conductive pillars formed over a carrier. A first semiconductor die is mounted over the carrier between the conductive pillars. An encapsulant is deposited over the first semiconductor die and carrier and around the conductive pillars. A recess is formed in a first surface of the encapsulant over the first semiconductor die. The recess has sloped or stepped sides. A first interconnect structure is formed over the first surface of the encapsulant. The first interconnect structure follows a contour of the recess in the encapsulant. The carrier is removed. A second interconnect structure is formed over a second surface of the encapsulant and first semiconductor die. The first and second interconnect structures are electrically connected to the conductive pillars. A second semiconductor die is mounted in the recess. A third semiconductor die is mounted over the recess and second semiconductor die.

Claims

1. A semiconductor device, comprising:

a first semiconductor die;

a first interconnect structure;

an encapsulant deposited over the first semiconductor die and first interconnect structure; and

a second interconnect structure disposed over the first semiconductor die, encapsulant, and first interconnect structure.

2. The semiconductor device of claim 1, wherein the first interconnect structure extends through the encapsulant.

3. The semiconductor device of claim 1, further including a second semiconductor die disposed over the first semiconductor die with the second semiconductor die electrically connected to the second interconnect structure through the first interconnect structure.

4. The semiconductor device of claim 1, wherein the first semiconductor die includes an electrical component and a mechanical component.

5. The semiconductor device of claim 1, wherein the first interconnect structure includes a conductive pillar or conductive via.

6. The semiconductor device of claim 1, further including a conductive layer formed over the first interconnect structure opposite the second interconnect structure.

7. A semiconductor device, comprising:

a first semiconductor die;

a first interconnect structure; and

an encapsulant deposited over the first semiconductor die, wherein the first interconnect structure extends through the encapsulant.

8. The semiconductor device of claim 7, further including a first conductive layer formed over the first interconnect structure.

9. The semiconductor device of claim 8, further including a second conductive layer electrically connected to the first conductive layer through the first interconnect structure.

10. The semiconductor device of claim 7, further including a second interconnect structure disposed over the first semiconductor die, encapsulant, and first interconnect structure.

11. The semiconductor device of claim 7, further including a second semiconductor die disposed over the first semiconductor die and electrically connected to the first interconnect structure.

12. The semiconductor device of claim 7, wherein the first semiconductor die includes an electrical component and a mechanical component.

13. The semiconductor device of claim 7, wherein the first interconnect structure includes a conductive pillar or conductive via.

14. A semiconductor device, comprising:

a first semiconductor die;

a first interconnect structure disposed adjacent to the first semiconductor die;

an encapsulant deposited over the first semiconductor die; and

a second interconnect structure disposed over the first semiconductor die.

15. The semiconductor device of claim 14, wherein the first interconnect structure extends through the encapsulant.

16. The semiconductor device of claim 14, further including a second semiconductor die disposed over the first interconnect structure.

17. The semiconductor device of claim 14, wherein the first semiconductor die includes an electrical component and a mechanical component.

18. The semiconductor device of claim 14, wherein the first interconnect structure includes a conductive pillar or conductive via.

19. The semiconductor device of claim 14, further including a conductive layer formed over the first interconnect structure.

20. A semiconductor device, comprising:

a first semiconductor die;

a first interconnect structure disposed adjacent to the first semiconductor die; and

an encapsulant deposited over the first semiconductor die.

21. The semiconductor device of claim 20, further including a second semiconductor die disposed over the first interconnect structure.

22. The semiconductor device of claim 20, wherein the first interconnect structure includes a conductive pillar or conductive via.

23. The semiconductor device of claim 20, further including a conductive layer formed over the first interconnect structure.

24. The semiconductor device of claim 20, further including a second interconnect structure formed over the first semiconductor die.

25. The semiconductor device of claim 20, wherein the first semiconductor die includes an electrical component and a mechanical component.