SEMICONDUCTOR DEVICE

• US 20170062445A1
• Filed: 07/18/2016
• Published: 03/02/2017
• Est. Priority Date: 08/26/2015
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: YAMASHITA, Tomohiro
• Granted Patent: US 10,043,814 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/42344 with at least one additional gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66818 the channel being thinned after patterning, e.g. sacrificial oxidation on fin
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7855 with at least two independent gates
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region

Abstract

A semiconductor device includes: a fin that is a portion of a semiconductor substrate, protrudes from a main surface of the semiconductor substrate, has a width in a first direction, and extends in a second direction; a control gate electrode that is arranged on the fin via a first gate insulating film and extends in the first direction; and a memory gate electrode that is arranged on the fin via a second gate insulating film and extends in the first direction. Further, a width of the fin in a region in which the memory gate electrode is arranged via the second gate insulating film having a film thickness larger than the first gate insulating film is smaller than a width of the fin in a region in which the control gate electrode is arranged via the first gate insulating film.

Claims

1. A semiconductor device comprising:

a semiconductor substrate having a main surface;

a protruding portion that is a portion of the semiconductor substrate, protrudes from the main surface, has a width in a first direction of the main surface, and extends in a second direction orthogonal to the first direction;

a first gate electrode that is arranged on the protruding portion via a first insulating film and extends in the first direction;

a second gate electrode that is arranged on the protruding portion via a second insulating film and extends in the first direction;

a third insulating film that is positioned between the first gate electrode and the second gate electrode; and

a first semiconductor region and a second semiconductor region that are formed in the protruding portion so as to sandwich the first gate electrode and the second gate electrode,

wherein a film thickness of the second insulating film is larger than a film thickness of the first insulating film, and

a first width of the protruding portion in a region overlapped with the second gate electrode is smaller than a second width of the protruding portion in a region overlapped with the first gate electrode.

2. The semiconductor device according to claim 1,

wherein the first insulating film includes a first silicon oxide film.

3. The semiconductor device according to claim 1,

wherein the second insulating film is a stacked film including a second silicon oxide film and a silicon nitride film on the second silicon oxide film.

4. The semiconductor device according to claim 3,

wherein the second insulating film includes a third silicon oxide film on the silicon nitride film.

5. The semiconductor device according to claim 1,

wherein the first gate electrode, the second gate electrode, the first semiconductor region and the second semiconductor region form one memory cell.

6. The semiconductor device according to claim 1 further comprising:

an element isolation film formed on the main surface of the semiconductor substrate,

wherein the element isolation film surrounds the protruding portion when seen in a plan view.

7. A semiconductor device comprising:

a semiconductor substrate having a main surface;

a first protruding portion that is a portion of the semiconductor substrate in a first region of the main surface, protrudes from the main surface, has a width in a first direction of the main surface, and extends in a second direction orthogonal to the first direction;

a second protruding portion that is a portion of the semiconductor substrate in a second region different from the first region, protrudes from the main surface, has a width in the first direction of the main surface, and extends in the second direction orthogonal to the first direction;

a first gate electrode that is arranged on the first protruding portion via a first insulating film and extends in the first direction;

a second gate electrode that is arranged on the second protruding portion via a second insulating film and extends in the first direction;

a first semiconductor region and a second semiconductor region that are formed in the first protruding portion so as to sandwich the first gate electrode; and

a third semiconductor region and a fourth semiconductor region that are formed in the second protruding portion so as to sandwich the second gate electrode,

wherein the first insulating film includes a charge accumulating layer, and

a first width of the first protruding portion in a region overlapped with the first gate electrode is larger than a second width of the second protruding portion in a region overlapped with the second gate electrode.

8. The semiconductor device according to claim 7,

wherein the first insulating film is a stacked film including a first silicon oxide film and a silicon nitride film on the first silicon oxide film.

9. The semiconductor device according to claim 8,

wherein the first gate electrode, the first insulating film, the first semiconductor region and the second semiconductor region form a first memory cell.

10. The semiconductor device according to claim 7 further comprising:

a first element isolation film that is formed on the main surface of the semiconductor substrate and surrounds the first protruding portion when seen in a plan view; and

a second element isolation film that is formed on the main surface of the semiconductor substrate and surrounds the second protruding portion when seen in a plan view.

11. The semiconductor device according to claim 10,

wherein a first height of the first protruding portion exposed from the first element isolation film in the region overlapped with the first gate electrode is larger than a second height of the second protruding portion exposed from the second element isolation film in the region overlapped with the second gate electrode.

12. The semiconductor device according to claim 11 further comprising:

a third gate electrode that is arranged on the first protruding portion via a third insulating film and extends in the first direction,

wherein a third width of the first protruding portion in a region overlapped with the third gate electrode is larger than the first width.

13. The semiconductor device according to claim 12,

wherein a third height of the first protruding portion exposed from the first element isolation film in the region overlapped with the third gate electrode is larger than the first height.

14. The semiconductor device according to claim 12,

wherein the first semiconductor region and the second semiconductor region are arranged so as to sandwich the first gate electrode and the third gate electrode, and

the first gate electrode, the first insulating film, the third gate electrode, the third insulating film, the first semiconductor region and the second semiconductor region form a second memory cell.

15. The semiconductor device according to claim 14,

wherein the second gate electrode, the second insulating film, the third semiconductor region and the fourth semiconductor region form a transistor.