ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME

• US 20170062712A1
• Filed: 11/16/2016
• Published: 03/02/2017
• Est. Priority Date: 06/05/2013
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: Choi, Won-Joon, Park, Ki-Seon, Dong, Cha-Deok, Lee, Bo-Mi, Kim, Guk-Cheon, Noh, Seung-Mo, Lee, Min-Suk, Park, Chan-Sik, Kim, Jae-Heon, Kim, Choi-Dong, Kim, Jae-Hong, Kim, Yang-Kon, Lim, Jong-Koo
• Granted Patent: US 10,490,741 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: H10N 50/01 Manufacture or treatment
• CPC Class Codes: H10N 50/10 Magnetoresistive devices
• CPC Class Codes: H10N 50/80 Constructional details
• CPC Class Codes: H10N 50/85 Magnetic active materials
• CPC Class Codes: H10N 70/011 Manufacture or treatment of multistable switching devices
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/882 Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
• CPC Class Codes: H10N 70/8833 Binary metal oxides, e.g. TaOx

Abstract

Methods, systems, and devices are disclosed for implementing semiconductor memory using variable resistance elements for storing data. In one aspect, an electronic device is provided to comprise a semiconductor memory unit including: a substrate; an interlayer dielectric layer disposed over the substrate; and a variable resistance element including a seed layer formed over the interlayer dielectric layer, a first magnetic layer formed over the seed layer, a tunnel barrier layer formed over the first magnetic layer, and a second magnetic layer formed over the tunnel barrier layer, wherein the seed layer includes a conductive material having a metallic property and an oxygen content of 1% to approximately 10%.

Claims

1. An electronic device comprising a semiconductor memory unit that includes:

a substrate;

an interlayer dielectric layer disposed over the substrate and having a recess;

a contact formed in the recess; and

a variable resistance element including a seed layer formed over the interlayer dielectric layer, a first magnetic layer formed over the seed layer, a tunnel barrier layer formed over the first magnetic layer, and a second magnetic layer formed over the tunnel barrier layer,

wherein the seed layer to improve the anisotropy energy of the first magnetic layer includes a conductive material having a metallic property and an oxygen content of 1% to approximately 10%.

2. The electronic device of claim 1, wherein the seed layer includes conductive hafnium silicate.

3. The electronic device of claim 1, wherein the variable resistance element further includes a bottom layer formed within the interlayer dielectric layer.

4. The electronic device of claim 3, wherein the bottom layer includes first and second material layers and a barrier layer interposed between the first and second material layers and the barrier layer has a dual phase structure.

5. The electronic device of claim 4, wherein the first material layer including HfN, TiN, MoN, ZrN, or MgO and the second material layer including AlN, AgI, ZnO, CdS, CdSe, a-SiC, GaN, or BN.

6. The electronic device of claim 1, wherein the semiconductor memory further includes:

a spacer formed on a sidewall of the variable resistance element.

7. The electronic device of claim 6, wherein the spacer including a metal having a higher electron affinity than a component included in the tunnel barrier layer, the first magnetic layer and second magnetic layer.

8. An electronic device comprising a semiconductor memory unit that includes:

a substrate;

an interlayer dielectric layer disposed over the substrate and having a recess;

a contact formed in a lower portion of the recess; and

a variable resistance element including a bottom layer having at least a portion formed in an upper portion of the recess within the interlayer dielectric layer, a first magnetic layer formed over the bottom layer, a tunnel barrier layer formed over the first magnetic layer and a second magnetic layer formed over the tunnel barrier layer,

wherein the bottom layer has a width greater than the contact, and the bottom layer includes a first material including HfN, TiN, MoN, ZrN, or MgO and a second material including AlN, AgI, ZnO, CdS, CdSe, a-SiC, GaN, or BN.

9. The electronic device of claim 8, wherein the variable resistance element further includes a seed layer including conductive hafnium silicate.

10. The electronic device of claim 8, wherein the semiconductor memory further includes:

a spacer formed on a sidewall of the remaining structure of the variable resistance element.

11. The electronic device of claim 10, wherein the spacer including a metal having a higher electron affinity than a component included in the tunnel barrier layer, the first magnetic layer and second magnetic layer.

12. The electronic device of claim 8, wherein the bottom layer includes a first part which is filled in the recess and a second part which protrudes out of the interlayer dielectric layer.

13. The electronic device of claim 8, wherein the bottom layer further includes a barrier layer interposed between the first and second metal layers and the barrier layer has a dual phase structure.

14. An electronic device comprising a semiconductor memory unit that includes:

a substrate;

an interlayer dielectric layer disposed over the substrate and having a recess;

a contact formed in the recess; and

a variable resistance element including a first part disposed over the contact in the interlayer dielectric layer, a second part disposed over the first part and protruding over the interlayer dielectric layer and a spacer formed over a sidewall of the second part,

wherein the spacer including a metal having a higher electron affinity than a component included in the second part of the variable resistance element, wherein the second part of the variable resistance element includes a first magnetic layer formed over the first part;

a tunnel barrier layer formed over the first magnetic layer; and

a second magnetic layer formed over the tunnel barrier layer.

15. The electronic device of claim 14, wherein the first part includes a first metal having a higher electron affinity than a component included in the second part.

16. The electronic device of claim 14, wherein the variable resistance element further includes a seed layer including conductive hafnium silicate.

17. The electronic device of claim 14, wherein the first part of the variable resistance element includes first and second metal layers and a barrier layer interposed between the first and second metal layers and the barrier layer has a dual phase structure.