PACKAGE PROGRAMMABLE DECOUPLING CAPACITOR ARRAY

• US 20170063355A1
• Filed: 08/28/2015
• Published: 03/02/2017
• Est. Priority Date: 08/28/2015
• Status: Active Grant

• Current Assignee: Ampere Computing LLC, MACOM Connectivity Solutions, LLC (MACOM Technology Solutions Holdings, Inc.)
• Original Assignee: Applied Micro Circuits Corporation (MACOM Technology Solutions Holdings, Inc.)
• Inventors: Thaik, Rich, Lambert, April, Plunkett, Jeremy, Yeung, Alfred
• Granted Patent: US 9,998,100 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/525 with adaptable interconnections
• CPC Class Codes: H01L 23/5382 Adaptable interconnections, e.g. for engineering changes
• CPC Class Codes: H01L 2924/15192 Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: H01L 2924/19105 in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H03K 5/1252 Suppression or limitation of noise or interference specially adapted for transmission systems H04B15/00, H04L25/08

Abstract

A semiconductor chip allows for a selected amount of on-die decoupling capacitance to be connected to a very-large-scale integrated circuit (VLSI) system after the circuit design is complete. The semiconductor chip comprises an integrated circuit disposed on a packaging substrate, and a power distribution network that is electrically connectable to the integrated circuit via a programmable connectivity array via the packaging substrate.

Claims

1. A semiconductor chip, comprising:

an integrated circuit disposed on a packaging substrate; and

a power distribution network that is electrically connectable to the integrated circuit via a programmable connectivity array via the packaging substrate the programmable connectivity array comprising an array of on-die programmable decoupling capacitors formed on the semiconductor chip.

3. The semiconductor chip of claim 1, wherein the array of on-die programmable decoupling capacitors and the power distribution network are integrated in the semiconductor chip.

4. The semiconductor chip of claim 1, wherein the array of on-die programmable decoupling capacitors comprises a plurality of discrete blocks of on-die programmable decoupling capacitors.

5. The semiconductor chip of claim 4, wherein a desired capacitance is obtainable by selectively connecting discrete blocks of the on-die programmable decoupling capacitors to the power distribution network and the integrated circuit via the packaging substrate.

6. The semiconductor chip of claim 5, wherein the array of on-die programmable decoupling capacitors is configured to serve as a band rejection filter or a notch filter.

7. The semiconductor chip of claim 6, wherein the capacitance of the band rejection filter is configured to suppress a resonant frequency of the semiconductor chip.

8. The semiconductor chip of claim 6, wherein the frequency of the band rejection filter is controllable by electrically connecting bumps disposed on the plurality of discrete blocks that are configured for connecting the plurality of discrete blocks to the power distribution network.

9. The semiconductor chip of claim 1, wherein the programmable connectivity array is variable by modifying the programmable connectivity array of the packaging substrate.

10. The semiconductor chip of claim 5, wherein unconnected blocks of the on-die programmable decoupling capacitors from the array of on-die programmable decoupling capacitors are connectable to alternative power distribution systems of the chip.

11. The semiconductor chip of claim 1, wherein the array of on-die programmable decoupling capacitors comprises a plurality of low priority decoupling capacitors.

12. The semiconductor chip of claim 1, further comprising a processor configured to perform one or more processing functions in connection with operation of the integrated circuit.

2. (canceled)

13. A method of suppressing supply noise in a semiconductor chip, comprising:

placing a programmable connectivity array physically near an integrated circuit embedded in a semiconductor chip, the programmable connectivity array comprising an array of on-die programmable decoupling capacitors formed on the semiconductor chip, and wherein the semiconductor chip is supported on a packaging substrate; and

supplying power to the integrated circuit via the programmable connectivity array through the packaging substrate.

14. The method of claim 13, wherein the placing comprises configuring the array of on-die programmable decoupling capacitors for a desired capacitance.

15. The method of claim 13, further comprising configuring the array of on-die programmable decoupling capacitors to serve as a band rejection filter or a notch filter in the integrated circuit.

16. The method of claim 13, wherein the array of on-die programmable programmable decoupling capacitors is integrated in the semiconductor chip.

17. The method of claim 13, wherein the array of on-die programmable programmable decoupling capacitors comprises a plurality of discrete blocks of programmable decoupling capacitors.

18. The method of claim 17, further comprising connecting discrete blocks of the on-die programmable decoupling capacitors to the integrated circuit and a power distribution network of the semiconductor chip to obtain a target capacitance.

19. A method of suppressing resonant peaks in an integrated circuit in a semiconductor chip, comprising:

supporting the semiconductor chip on a packaging substrate; and

supplying power to the integrated circuit via a programmable connectivity array through the packaging substrate, the programmable connectivity array comprising an array of on-die programmable decoupling capacitors that are formed on the semiconductor chip, and wherein the programmable connectivity array is placed physically near the integrated circuit.

20. The method of claim 19, wherein the array of on-die programmable decoupling capacitors is configurable for a desired capacitance.

21. The method of claim 19, wherein the array of on-die programmable decoupling capacitors comprises a plurality of discrete blocks of on-die programmable decoupling capacitors.