SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

• US 20170066646A1
• Filed: 09/03/2015
• Published: 03/09/2017
• Est. Priority Date: 09/03/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: LAI, FEI-LUNG, LIN, SHIANG-CHI, CHENG, CHUN-WEN, CHU, CHIA-HUA
• Granted Patent: US 9,567,209 B1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: B81B 2201/0214 Biosensors; Chemical sensors
• CPC Class Codes: B81B 2203/0127 Diaphragms, i.e. structures separating two media that can control the passage from one medium to another; Membranes, i.e. diaphragms with filtering function
• CPC Class Codes: B81B 2203/0315 Cavities
• CPC Class Codes: B81B 2203/04 Electrodes
• CPC Class Codes: B81B 2207/012 the micromechanical device and the control or processing electronics being separate parts in the same package
• CPC Class Codes: B81B 2207/07 Interconnects
• CPC Class Codes: B81B 7/007 Interconnections between the MEMS and external electrical signals
• CPC Class Codes: B81C 1/0015 Cantilevers switches using MEMS H01H1/0036; electrostatic relays using micromechanics H01H59/0009; microelectro-mechanical resonators H03H9/02244
• CPC Class Codes: B81C 1/00158 Diaphragms, membranes manufacture process for semi-permeable inorganic membranes B01D67/0039
• CPC Class Codes: B81C 1/00182 Arrangements of deformable or non-deformable structures, e.g. membrane and cavity for use in a transducer
• CPC Class Codes: B81C 1/00301 Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
• CPC Class Codes: B81C 2203/035 Soldering
• CPC Class Codes: B81C 2203/0792 Forming interconnections between the electronic processing unit and the micromechanical structure
• CPC Class Codes: G01L 9/0041 Transmitting or indicating the displacement of flexible diaphragms
• CPC Class Codes: G01L 9/0042 Constructional details associated with semiconductive diaphragm sensors, e.g. etching, or constructional details of non-semiconductive diaphragms details about the integration or bonding of piezoresistor in or on the diaphragm G01L9/0052 and G01L9/0057 respectively
• CPC Class Codes: G01L 9/0044 Constructional details of non-semiconductive diaphragms
• CPC Class Codes: G01L 9/0045 Diaphragm associated with a buried cavity
• CPC Class Codes: G01L 9/0048 Details about the mounting of the diaphragm to its support or about the diaphragm edges, e.g. notches, round shapes for stress relief
• CPC Class Codes: G01N 27/123 for controlling the temperature temperature control per se G05D23/00

Abstract

A semiconductor structure includes a first device and a second device. The first device includes a first substrate, a plurality of vias passing through the first substrate and filled with a conductive or semiconductive material and a first oxide layer surrounding the conductive or semiconductive material, a cavity surrounded by the first substrate, a metallic material disposed over the first surface, a second oxide layer disposed over the second surface, a membrane disposed over the second oxide layer and the cavity, a heater disposed within the membrane, a sensing electrode disposed over the membrane and the heater, and a sensing material disposed over the cavity and contacting with the sensing electrode. The second device includes a second substrate, and a bonding structure disposed over the second substrate. The metallic material is bonded with the bonding structure to integrate the first device with the second device.

Claims

1. A semiconductor structure, comprising:

a first device comprising;

a first substrate including a first surface, a second surface opposite to the first surface, and a plurality of vias passing through the first substrate and filled with a conductive or semiconductive material and a first oxide layer surrounding the conductive or semiconductive material;

a cavity surrounded by the first substrate;

a metallic material disposed over the first surface, covering some of the plurality of vias, and electrically connecting with the first substrate;

a second oxide layer disposed over the second surface;

a membrane disposed over the second oxide layer and the cavity;

a heater disposed within the membrane and electrically connected with the first substrate through the oxide layer;

a sensing electrode disposed over the membrane and the heater; and

a sensing material disposed over the cavity and contacting with the sensing electrode, and

a second device comprising;

a second substrate; and

a bonding structure disposed over the second substrate,

wherein the metallic material is bonded with the bonding structure to integrate the first device with the second device.

2. The semiconductor structure of claim 1, wherein the heater includes tungsten alloy, tungsten silicide (WSi), titanium tungsten (TiW), titanium aluminum nitride (TiAlN), tantalum aluminum (TaAl), chromium (Cr), platinum (Pt), titanium nitride (TiN), molybdenum (Mo), polysilicon, silicon carbide (SiC), tantalum nitride (TaN) or tantalum oxide (TaO).

3. The semiconductor structure of claim 1, wherein the metallic material includes aluminum or copper, or the bonding structure includes germanium.

4. The semiconductor structure of claim 1, wherein a portion of the first substrate is surrounded by the first oxide layer and the conductive or semiconductive material, and the conductive or semiconductive material is isolated from the first substrate by the first oxide layer.

5. The semiconductor structure of claim 1, wherein the sensing electrode is configured to sense a change of resistance of the sensing material, and the resistance of the sensing material is varied by a chemical reaction between the sensing material and a predetermined material.

6. The semiconductor structure of claim 1, wherein the heater is extended laterally or vertically along the membrane, or the sensing electrode is extended laterally or vertically over a surface of the membrane.

7. The semiconductor structure of claim 1, wherein the conductive or semiconductive material includes polysilicon.

8. The semiconductor structure of claim 1, wherein the membrane includes silicon, silicon dioxide (SiO₂) or silicon nitride (SiN), silicon carbide (SiC), porous silicon or composite film.

9. The semiconductor structure of claim 1, wherein the sensing electrode includes tungsten alloy, titanium tungsten (TiW), titanium aluminum nitride (TiAlN), tantalum aluminum (TaAl), titanium, titanium nitride (TiN), tantalum, tantalum nitride (TaN), tantalum oxide (TaO), platinum (Pt) or tantalum silicon nitride (TaSiN).

10. The semiconductor structure of claim 1, wherein the sensing material includes tin dioxide (SnO₂), zine oxide (ZnO) or indium oxide (In₂O₃).

11. A semiconductor structure, comprising:

a CMOS substrate;

an intermetallic dielectric (IMD) layer disposed over the CMOS substrate;

a bonding structure disposed over the IMD layer;

a MEMS substrate including a first surface facing the CMOS substrate and a second surface opposite to the first surface;

a metallic material disposed over the first surface;

a cavity surrounded by the MEMS substrate;

a polysilicon disposed within the MEMS substrate;

a first oxide layer disposed between the polysilicon and the MEMS substrate;

a second oxide layer disposed over the second surface;

a membrane disposed over the second oxide layer and the cavity;

a heater disposed within the membrane and electrically connected with the MEMS substrate;

a sensing electrode disposed over the membrane and the heater, and electrically connected with the MEMS substrate; and

a sensing material covering a portion of the sensing electrode,

wherein the CMOS substrate and the MEMS substrate are integrated by bonding the metallic material with the bonding structure and electrically connecting the CMOS substrate with the MEMS substrate.

12. The semiconductor structure of claim 11, further comprising:

an isolation layer disposed over the CMOS substrate and configured to thermally isolate the CMOS substrate from the MEMS substrate;

or

an interconnect structure including a via portion passing through the isolation layer and contacted with the IMD layer, and an elongated portion extending over and along the isolation layer and configured to receive the bonding structure;

or

a third oxide layer disposed over the isolation layer and between the via portion and the isolation layer.

13. The semiconductor structure of claim 11, wherein the bonding structure is a bond pad.

14. The semiconductor structure of claim 11, wherein the second oxide layer is disposed over the cavity.

15. The semiconductor structure of claim 11, wherein the heater is configured to provide an operating temperature of about 300°

C. to about 800°

C. to facilitate sensation of a predetermined gas by the sensing electrode, or the heater has a width of about 0.1 um to about 30 um.

16. A method of manufacturing a semiconductor structure, comprising:

receiving a first substrate including a first surface, a second surface opposite to the first surface, a plurality of vias extending from the second surface towards the first surface and filled with a conductive or semiconductive material, a first oxide layer disposed between the first substrate and the conductive or semiconductive material, and a second oxide layer disposed over the second surface;

disposing and patterning a first membrane layer over the second oxide layer;

disposing and patterning a heater over the first membrane layer;

disposing and patterning a second membrane layer over the heater and the first membrane layer;

disposing a sensing electrode over the second membrane layer;

disposing a sacrificial oxide over the sensing electrode and the second membrane layer;

removing some of the first substrate from the first surface to expose the conductive or semiconductive material;

disposing a metallic material over the first surface and the plurality of vias;

forming a cavity surrounded by the first substrate;

receiving a second substrate including a bonding structure disposed over the second substrate;

bonding the metallic material with the bonding structure;

removing the sacrificial oxide; and

disposing a sensing material over the sensing electrode.

17. The method of claim 16, wherein the forming the cavity includes etching the first substrate from the first surface to expose the first membrane layer or the second oxide layer.

18. The method of claim 16, wherein the bonding the metallic material with the bonding structure includes eutectic bonding operations.

19. The method of claim 16, wherein the removing some of the first substrate includes grinding the first surface towards the second surface.

20. The method of claim 16, further comprising:

forming an intermetallic dielectric (IMD) layer over the second substrate;

disposing and patterning an isolation layer over the second substrate;

disposing a third oxide layer conformal to the isolation layer;

forming an interconnect structure including a via portion contacting with the IMD layer, and an elongated portion disposed along the third oxide layer and coupled with the bonding structure.