SEMICONDUCTOR STORAGE DEVICE AND CONTROL METHOD OF SEMICONDUCTOR STORAGE DEVICE

• US 20170069373A1
• Filed: 12/10/2015
• Published: 03/09/2017
• Est. Priority Date: 09/09/2015
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: SUGIMOTO, Takeshi
• Granted Patent: US 9,858,998 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 13/0023 Address circuits or decoders
• CPC Class Codes: G11C 13/0028 Word-line or row circuits
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0061 Timing circuits or methods
• CPC Class Codes: G11C 2013/0054 Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell
• CPC Class Codes: G11C 2013/0057 Read done in two steps, e.g. wherein the cell is read twice and one of the two read values serving as a reference value

Abstract

According to one embodiment, there is provided a semiconductor storage device including N word lines, M bit lines, multiple memory cells, and a read circuit. N is an integer of four or greater. M is an integer of two or greater. The M bit lines intersect with the word lines. The multiple memory cells are placed at positions where the word lines and the bit lines intersect. The memory cell stores binary data. The read circuit is connected to the M bit lines. The read circuit is able to detect levels of a multi-ary signal.

Claims

1. A semiconductor storage device comprising:

N word lines, N being an integer of four or greater;

M bit lines that intersect with the word lines, M being an integer of two or greater;

multiple memory cells placed at positions where the word lines and the bit lines intersect, the memory cell storing binary data; and

a read circuit connected to the M bit lines, the read circuit being able to detect levels of a multi-ary signal.

2. The semiconductor storage device according to claim 1, wherein

the multiple memory cells have a variable resistance element that can transition between a high resistance state and a low resistance state.

3. The semiconductor storage device according to claim 1, further comprising a control circuit that can select K word lines in parallel, K being an integer of three or greater and being smaller than N.

4. The semiconductor storage device according to claim 3, wherein

the control circuit has N decoding circuits corresponding to the N word lines, and

wherein the decoding circuits has:

(K+1) sub-decoding circuits, K being an integer of three or greater and being smaller than N; and

a combining circuit connected between the (K+1) sub-decoding circuits and the word line.

5. The semiconductor storage device according to claim 1, wherein

the read circuit can detect levels of a (K+1)-ary signal on a bit line selected from the M bit lines, K being an integer of three or greater and being smaller than N.

6. The semiconductor storage device according to claim 1, wherein

the read circuit has M sense amplifiers corresponding to the M bit lines, and

wherein the sense amplifiers has:

a current mirror circuit group connected to the bit line; and

K detection circuits connected to the current mirror circuit group that can detect different signal levels, K being an integer of three or greater and being smaller than N.

7. The semiconductor storage device according to claim 6, wherein

the detection circuits has:

an input node connected to the current mirror circuit group;

a capacitance element electrically connected at one end to the input node and an output node; and

a current source connected to the input node, and

wherein the K detection circuits are different in drive capability of the current source.

8. The semiconductor storage device according to claim 6, wherein

the detection circuits has:

an input node connected to the current mirror circuit group;

a current source connected to the input node; and

a comparator that compares the potential on the input node and a reference potential to output the comparing result onto an output node, and

wherein the K detection circuits are equivalent in drive capability of the current source and are supplied with reference potentials of different levels.

9. The semiconductor storage device according to claim 1, wherein

the read circuit detects K times the level of the signal from (K+1) memory cells, as candidates for selection, on a bit line selected from the M bit lines, K being an integer of three or greater and being smaller than N.

10. The semiconductor storage device according to claim 9, further comprising a control circuit that can select K word lines in parallel, K being an integer of three or greater and being smaller than N,

wherein the read circuit detects the level of the signal output from K selected memory cells on the selected bit line with K word lines being selected by the control circuit.

11. The semiconductor storage device according to claim 9, further comprising a control circuit that can select K word lines in parallel, K being an integer of three or greater and being smaller than N,

wherein the control circuit determines (K+1) word lines from among the N word lines to be candidates for selection and performs selection operation of K word lines from among the (K+1) word lines K times such that a non-selected word line is different for the K times, and

wherein the read circuit detects the level of the signal output from K memory cells selected from among the (K+1) memory cells K times while the non-selected memory cell is different for the K times.

12. The semiconductor storage device according to claim 11, wherein

in selection operations of the K times, the control circuit selects one of the (K+1) word lines fixedly and selects (K−

1) word lines from remaining K word lines.

13. The semiconductor storage device according to claim 11, wherein

the control circuit has N decoding circuits corresponding to the N word lines, and

wherein the decoding circuits has:

(K+1) sub-decoding circuits corresponding to the (K+1) word lines as candidates for selection; and

a combining circuit that combines signals output from the (K+1) sub-decoding circuits.

14. The semiconductor storage device according to claim 13, wherein

the sub-decoding circuit decodes a combination of address signals and a control signal to decide on the non-selected word line.

15. The semiconductor storage device according to claim 9, further comprising:

a hold circuit that holds detection results for the signal levels of the K times; and

a recovery circuit that recovers data of the (K+1) memory cells based on the detection results for signal levels of the K times.

16. The semiconductor storage device according to claim 15, wherein

the recovery circuit converts a combination of the K times of the signal level into (K+1)-bit data to recover data of the (K+1) memory cells.

17. A control method of a semiconductor storage device which has N word lines, M bit lines that intersect with the word lines, and multiple memory cells placed at positions where the word lines and the bit lines intersect, N being an integer of four or greater, M being an integer of two or greater, the memory cell storing binary data, the control method comprising:

selecting K word lines in parallel from among the N word lines, K being an integer of three or greater and being smaller than N; and

detecting a level of a multi-ary signal output from K selected memory cells on one bit line selected from among the M bit lines in a state where the K word lines are selected.

18. The control method of the semiconductor storage device according to claim 17, wherein

the selecting includes determining (K+1) word lines from among the N word lines to be candidates for selection and performing selection operation of K word lines from among the (K+1) word lines K times such that a non-selected word line is different for the K times, and

wherein the detecting includes detecting the level of the signal output from K memory cells selected from among the (K+1) memory cells K times while the non-selected memory cell is different for the K times.

19. The control method of the semiconductor storage device according to claim 18, wherein

the selecting includes, in selection operations of the K times, selecting one of the (K+1) word lines fixedly and selecting (K−

1) word lines from remaining K word lines.

20. The control method of the semiconductor storage device according to claim 19, further comprising:

holding detection results for signal levels of the K times; and

recovering data of the (K+1) memory cells based on the detection results for signal levels of the K times.