HOST DEVICE AND MEMORY DEVICE

• US 20170069395A1
• Filed: 03/07/2016
• Published: 03/09/2017
• Est. Priority Date: 09/09/2015
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: YAO, Hiroshi, SUZUKI, Riki, HIDA, Toshikatsu
• Granted Patent: US 10,665,305 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 1/3225 of memory devices
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 11/0721 within a central processing unit [CPU]
• CPC Class Codes: G06F 11/0727 in a storage system, e.g. in a DASD or network based storage system drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

According to one embodiment, a controller of a host causes a memory device to transit from a first state that is an active state to a second state that is a sleep state in a case where there is no access to the memory device for a first time or more. The controller causes the memory device to transit from the second state to the first state in a case where there is no access to the memory device for a second time or more after the transition to the second state.

Claims

1. A host device connectable to a memory device including a nonvolatile memory, the nonvolatile memory including a plurality of blocks, the memory device executing patrol read, the patrol read including reading first data, testing the read first data, and refreshing data stored inside a block including second data that is not successful in the test among the read first data, the first data being data of a certain unit stored in the nonvolatile memory,

the host device including a controller configured to:

in a case where the controller does not access to the memory device for a first time or more, cause the memory device to transit from a first state to a second state, the first state being an active state, the first state being capable of executing the patrol read, the second state being a sleep state; and

in a case where the controller does not access to the memory device for a second time or more after the transition to the second state, cause the memory device to transit from the second state to the first state.

2. The host device according to claim 1, wherein

the first state is a state in which power supply to the memory device is turned off, and

the second state is a state in which power supply to the memory device is turned on.

3. The host device according to claim 1, wherein the memory device can execute the patrol read in the first state but cannot execute the patrol read in the second state.

4. The host device according to claim 1, wherein the controller instructs the memory device to execute the patrol read in a case where the memory device is caused to transit from the second state to the first state.

5. The host device according to claim 1, wherein the second time is set based on a guarantee time of data retention of the memory device.

6. The host device according to claim 1, wherein the controller determines whether the memory device executes an internal process based on information transmitted from the memory device and causes the memory device to transit from the first state to the second state in a case where the internal process is not executed.

7. The host device according to claim 6, wherein the internal process includes the patrol read and garbage collection.

8. The host device according to claim 1, wherein the controller determines whether the patrol read is necessary for the memory device based on information transmitted from the memory device and causes the memory device to transit from the first state to the second state in a case where the patrol read is determined not to be necessary.

9. The host device according to claim 1, wherein the controller sets the first time to a time that is a time required for the patrol read or more.

10. The host device according to claim 1, wherein, after causing the memory device to transit from the second state to the first state, the controller does not transmit a command other than a read command and a write command.

11. The host device according to claim 1, wherein, after causing the memory device to transit from the second state to the first state, the controller transmits a command for reading an accessible entire area of the nonvolatile memory.

12. The host device according to claim 1, wherein, in a case where the memory device is in the second state at certain time, the controller causes the memory device to transit to the first state.

13. A memory device connectable to a host device, the memory device comprising:

a nonvolatile memory including a plurality of blocks; and

a controller configured to;

execute patrol read, the patrol read including reading first data, testing the read first data, and refreshing data stored inside a block including second data that is not successful in the test among the read first data, the first data being data of a certain unit stored in the nonvolatile memory; and

notify start and end of the patrol read to the host device.

14. The memory device according to claim 13, wherein the controller notifies information representing necessity/no-necessary of the patrol read to the host device.

15. The memory device according to claim 13, wherein, when the controller notifies the start of the patrol read to the host device, the controller notifies a scheduled end time of the patrol read to the host device.

16. The memory device according to claim 13, wherein the controller calculates an interval time from the end of the patrol read to next startup of the patrol read and notifies information representing the calculated interval time to the host device.

17. The memory device according to claim 13, wherein the controller selects a ratio of a target area of the test to an area of the nonvolatile memory and notifies information representing the selected ratio to the host device.

18. The memory device according to claim 13,

wherein the block includes a plurality of memory cells, and

wherein the controller

executes first refreshing in a case where the number of error bits of a first block is more than a first threshold, the first refreshing including reprogramming a plurality of second memory cells among a plurality of first memory cells included in the first block,

executes second refreshing in a case where the number of error bits of the first block is more than a second threshold, the second threshold being larger than the first threshold, the second refreshing including moving data of the first block to a second block excluding the first block, and

notifies, to the host device, one of two refreshings, the first refreshing and second refreshing, to be executed.

19. The memory device according to claim 13,

wherein the block includes a plurality of memory cells, and

wherein the controller

executes first refreshing in a case where the number of error bits of a first block is more than a first threshold, the first refreshing including reprogramming a plurality of second memory cells among a plurality of first memory cells included in the first block,

executes second refreshing in a case where the number of error bits of the first block is more than a second threshold, the second threshold being larger than the first threshold, the second refreshing including reading data of the first block, erasing the first block, and writing the read data into the erased first block,

executes third refreshing in a case where the number of error bits of the first block is more than a third threshold, the third threshold being larger than the second threshold, the third refreshing including moving data of the first block to a second block excluding the first block, and

notifies, to the host device, refreshing to be executed among the first refreshing, the second refreshing, and the third refreshing.