METHOD FOR FABRICATING SEMICONDUCTOR DEVICE

• US 20170069543A1
• Filed: 10/15/2015
• Published: 03/09/2017
• Est. Priority Date: 09/03/2015
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Chang, Ching-Yu, Lin, Chun-Hao, Feng, Li-Wei, Tsai, Shih-Hung, Fu, Ssu-I, Jenq, Jyh-Shyang, Lin, Chien-Ting, Chen, Yi-Ren, Hsieh, Shou-Wei, Chen, Hsin-Yu
• Granted Patent: US 9,627,268 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02129 the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 29/66803 with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants

Abstract

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a fin-shaped structure thereon and a shallow trench isolation (STI) around the fin-shaped structure, in which the fin-shaped structure has a top portion and a bottom portion; forming a first doped layer on the STI and the top portion; and performing a first anneal process.

Claims

1-14. -14. (canceled)

15. A method for fabricating semiconductor device, comprising:

providing a substrate having a first region and a second region;

forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region;

forming a shallow trench isolation (STI) around the first fin-shaped structure and the second fin-shaped structure so that each of the first fin-shaped structure and the second fin-shaped structure is divided into a top portion and a bottom portion;

forming a first doped layer on the STI and on the top portion of the second fin-shaped structure;

forming a second doped layer on the STI and the top portion of the first fin-shaped structure, wherein the first doped layer and the second doped layer comprise dopants of same type; and

performing an anneal process.

16. The method of claim 15, further comprising:

forming the first doped layer and a first liner on the STI, the first fin-shaped structure, and the second fin-shaped structure;

removing the first liner and the first doped layer from the first region;

forming the second doped layer on the STI, the first fin-shaped structure, and the first liner; and

performing the anneal process.

17. The method of claim 15, wherein the dopant concentration of the first doped layer is higher than the dopant concentration of the second doped layer.

18. The method of claim 15, wherein the first doped layer and the second doped layer comprise borosilicate glass (BSG).

19. The method of claim 15, wherein the first doped layer and the second doped layer comprise phosphosilicate glass (PSG).