METHODS OF FORMING CMOS BASED INTEGRATED CIRCUIT PRODUCTS USING DISPOSABLE SPACERS

• US 20170069547A1
• Filed: 09/04/2015
• Published: 03/09/2017
• Est. Priority Date: 09/04/2015
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Peng, Wen Pin, Chi, Min-hwa, Derderian, Garo Jacques
• Granted Patent: US 9,704,759 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/0206 during, before or after processing of insulating layers
• CPC Class Codes: H01L 21/02252 formation by plasma treatment, e.g. plasma oxidation of the substrate after treatment of an insulating film by plasma H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/0234 treatment by exposure to a plasma
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

Disclosed herein is a method of forming a CMOS integrated circuit product (comprised of first and second opposite type transistors) that includes forming a first spacer proximate both the first and second gate structures, forming an initial second spacer proximate the first spacer of the first transistor and a layer of second spacer material above the second transistor, and forming first raised epi semiconductor material source/drain regions for the first transistor. Thereafter, performing a first surface oxidation process so as to selectively form a hydrophilic material on exposed surfaces of the first raised epi semiconductor material and performing an etching process on both the transistors so as to remove the initial second spacer and the layer of second spacer material.

Claims

1. A method of forming a CMOS integrated circuit product comprised of a first transistor of a first type and a second transistor of a second type formed on a substrate, wherein said second type is opposite to said first type, comprising:

forming a first gate structure for said first transistor and a second gate structure for said second transistor;

forming a first spacer proximate both said first and second gate structures;

forming an initial second spacer proximate said first spacer of said first transistor and a layer of second spacer material above said second transistor;

forming first raised epi semiconductor material source/drain regions for said first transistor;

performing a first surface oxidation process so as to selectively form a hydrophilic material on exposed surfaces of said first raised epi semiconductor material source/drain regions that is more hydrophilic that that of said semiconductor material of said first raised epi semiconductor material source/drain regions; and

performing a first etching process on both said first and second transistors so as to completely remove said initial second spacer from said first transistor and said layer of second spacer material above said second transistor, while leaving said first spacer in position on both said first and second transistors.

2. The method of claim 1, further comprising:

forming an initial third spacer proximate said first spacer of said second transistor and a layer of third spacer material above said first transistor;

forming second raised epi semiconductor material source/drain regions for said second transistor;

performing a second surface oxidation process so as to form a hydrophilic material on exposed surfaces of said second raised epi semiconductor material source/drain regions that is more hydrophilic that that of said semiconductor material of said second raised epi semiconductor material source/drain regions; and

performing a second etching process on both said first and second transistors so as to completely remove said initial third spacer from said second transistor and said layer of third spacer material above said first transistor, while leaving said first spacer in position on both said first and second transistors.

3. The method of claim 2, wherein forming said initial second spacer proximate said first spacer of both said first and second transistors comprises forming said initial second spacer on and in contact with said first spacer of both said first and second transistors.

4. The method of claim 1, wherein forming said first spacer comprises forming said first spacer from a material having a k value of less than 7.8.

5. The method of claim 4, wherein forming said initial second spacer comprises forming said initial second spacer from silicon nitride.

6. The method of claim 1, wherein said first spacers are comprised of SiCON and both said initial second spacer and said initial third spacer are comprised of silicon nitride.

7. The method of claim 1, wherein said initial second spacer is made of silicon nitride and wherein performing said first etching process comprises performing a wet etching process using H₃PO₄ as an etchant.

8. The method of claim 1, wherein, after forming said initial second spacer for said first transistor, and prior to forming said first raised epi semiconductor material source/drain regions for said first transistor, the method further comprises:

forming a plurality of first source/drain cavities in said substrate adjacent said first gate structure of said first transistor, wherein an uppermost inner edge of said plurality of first source/drain cavities are self-aligned with said initial second spacer in said first transistor; and

forming said first raised epi semiconductor material source/drain regions in said first source/drain cavities.

9. The method of claim 2, wherein, after forming said initial third spacer for said second transistor, and prior to forming said second raised epi semiconductor material source/drain regions for said second transistor, the method further comprises:

forming a plurality of second source/drain cavities in said substrate adjacent said gate structure of said second transistor, wherein an uppermost inner edge of said plurality of second source/drain cavities are self-aligned with said initial third spacer in said second transistor; and

forming said second raised epi semiconductor material source/drain regions in said second source/drain cavities.

10. The method of claim 1, wherein said first surface oxidation process is performed prior to performing said first etching process so as to completely remove said initial second spacer from said first transistor.

11. The method of claim 1, wherein said hydrophilic material is silicon dioxide.

12. The method of claim 1, wherein performing said first surface oxidation process to form said hydrophilic material comprises performing an oxygen-based plasma treatment process.

13. The method of claim 1, wherein performing said first surface oxidation process to form said hydrophilic material comprises performing a wet cleaning process using SPM.

14. The method of claim 1, wherein said first transistor is a PMOS transistor and said second transistor is an NMOS transistor.

15. A method of forming a CMOS integrated circuit product comprised of a first transistor of a first type and a second transistor of a second type formed on a substrate, wherein said second type is opposite to said first type, comprising:

forming a first gate structure for said first transistor and a second gate structure for said second transistor;

forming a first spacer proximate both said first and second gate structures, wherein said first spacer comprises a material having a k value of less than 7.8;

forming an initial second spacer proximate and in contact with said first spacer of said first transistor and a layer of second spacer material above said second transistor, wherein said initial second spacer is made of silicon nitride;

forming first raised epi semiconductor material source/drain regions for said first transistor;

performing a first surface oxidation process so as to selectively form a first substantially uniform layer of silicon dioxide on exposed surfaces of said first raised epi semiconductor material source/drain regions; and

performing a first etching process on both said first and second transistors so as to completely remove said initial second spacer from said first transistor and said layer of second spacer material above said second transistor, while leaving said first spacer in position on both said first and second transistors.

16. The method of claim 15, further comprising:

forming an initial third spacer proximate and in contact with said first spacer of said second transistor and a layer of third spacer material above said first transistor, wherein said initial third spacer is made of silicon nitride;

forming second raised epi semiconductor material source/drain regions for said second transistor;

performing a second surface oxidation process so as to form a second substantially uniform layer of silicon dioxide on exposed surfaces of said second raised epi semiconductor material source/drain regions; and

performing a second etching process on both said first and second transistors so as to completely remove said initial third spacer from said second transistor and said layer of third spacer material above said first transistor, while leaving said first spacer in position on both said first and second transistors.

17. The method of claim 15, wherein said first spacers are comprised of SiCON.

18. The method of claim 15, wherein performing said first etching process comprises performing a wet etching process using H₃PO₄ as an etchant.

19. The method of claim 15, wherein, after forming said initial second spacer for said first transistor, and prior to forming said first raised epi semiconductor material source/drain regions for said first transistor, the method further comprises:

forming a plurality of first source/drain cavities in said substrate adjacent said first gate structure of said first transistor, wherein an uppermost inner edge of said plurality of first source/drain cavities are self-aligned with said initial second spacer in said first transistor; and

forming said first raised epi semiconductor material source/drain regions in said first source/drain cavities.

20. The method of claim 16, wherein, after forming said initial third spacer for said second transistor, and prior to forming said second raised epi semiconductor material source/drain regions for said second transistor, the method further comprises:

forming a plurality of second source/drain cavities in said substrate adjacent said gate structure of said second transistor, wherein an uppermost inner edge of said plurality of said second source/drain cavities are self-aligned with said initial third spacer in said second transistor; and

forming said second raised epi semiconductor material source/drain regions in said second source/drain cavities.

21. The method of claim 15, wherein said first surface oxidation process is performed prior to performing said first etching process so as to completely remove said initial second spacer from said first transistor.

22. The method of claim 15, wherein performing said first surface oxidation process comprises performing an oxygen-based plasma treatment process.

23. The method of claim 15, wherein performing said first surface oxidation process comprises performing a wet cleaning process using SPM.