METHOD FOR MANUFACTURING A TRANSISTOR HAVING A SHARP JUNCTION BY FORMING RAISED SOURCE-DRAIN REGIONS BEFORE FORMING GATE REGIONS AND CORRESPONDING TRANSISTOR PRODUCED BY SAID METHOD

• US 20170069661A1
• Filed: 10/20/2015
• Published: 03/09/2017
• Est. Priority Date: 09/04/2015
• Status: Active Grant

• Current Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Inventors: Zhang, John Hongguang
• Granted Patent: US 9,685,456 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02546 Arsenides
• CPC Class Codes: H01L 21/02675 using laser beams
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/76283 Lateral isolation by refilling of trenches with dielectric material
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/20 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 29/66522 with an active layer made of a group 13/15 material H01L29/66446 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location

Abstract

A transistor device is fabricated by growing an epitaxial layer of semiconductor material on a semiconductor layer and forming an opening extending through the epitaxial layer at a position where a gate is to be located. This opening provides, from the epitaxial layer, a source epitaxial region on one side of the opening and a drain epitaxial region on an opposite side of the opening. The source epitaxial region and a first portion of the semiconductor layer underlying the source epitaxial region are then converted into a transistor source region. Additionally, the drain epitaxial region and a second portion of the semiconductor layer underlying the drain epitaxial region are converted into a transistor drain region. A third portion of the semiconductor layer between the transistor source and drain regions forms a transistor channel region. A transistor gate electrode is then formed in the opening above the transistor channel region.

Claims

1. A method, comprising:

growing an epitaxial layer of semiconductor material on a semiconductor layer;

forming an opening extending through said epitaxial layer of semiconductor material at a position where a transistor gate is to be located to provide, from said epitaxial layer of semiconductor material, a source epitaxial region on one side of said opening and a drain epitaxial region on an opposite side of said opening;

applying an anneal temperature to both the source epitaxial region and a first portion of the semiconductor layer underlying the source epitaxial region to convert the source epitaxial region and the first portion into a transistor source region;

applying an anneal temperature to both the drain epitaxial region and a second portion of the semiconductor layer underlying the drain epitaxial region to convert the drain epitaxial region and the second portion into a transistor drain region;

wherein a third portion of the semiconductor layer between the transistor source region and transistor drain region forms a transistor channel region; and

forming a transistor gate electrode in said opening above the transistor channel region.

2. The method of claim 1, further comprising forming trench isolations to delimit an active region of said semiconductor layer.

3. The method of claim 1, wherein the semiconductor layer is an upper semiconductor layer of a silicon on insulator (SOI) substrate.

4. The method of claim 1, further comprising:

forming a lower semiconductor layer;

forming an intervening layer on the lower semiconductor layer;

forming the semiconductor layer on the intervening layer; and

removing material of the intervening layer to form a cavity under the semiconductor layer.

5. The method of claim 4, wherein the semiconductor layer and lower semiconductor layer are made of a same semiconductor material.

6. The method of claim 5, wherein the epitaxial layer is made of said same semiconductor material.

7. The method of claim 6, wherein the semiconductor material is selected from the group consisting of a silicon-germanium material and an indium-gallium-arsenic material.

8. The method of claim 4, further comprising forming a substrate with a stress released semiconductor layer, said lower semiconductor layer comprising a first portion of said stress released semiconductor layer.

9. The method of claim 4, further comprising:

forming a substrate with a stress released semiconductor layer;

recessing a portion of said stress released semiconductor layer; and

wherein the semiconductor layer, the intervening layer and the lower semiconductor layer are formed in the recessed portion.

10. The method of claim 1, wherein forming the opening comprises:

forming a dielectric layer over the epitaxial layer of semiconductor material;

forming a first opening extending through the dielectric layer at the position where the gate is to be located;

forming sidewall spacers on side walls of the first opening to define a second opening; and

extending the second opening through said epitaxial layer of semiconductor material to form said opening.

11. The method of claim 1, wherein forming the opening comprises:

forming a sacrificial layer over the epitaxial layer of semiconductor material;

patterning the sacrificial layer to define a dummy gate at the position where the gate is to be located;

forming sidewall spacers on side walls of the dummy gate;

removing the dummy gate between the sidewall spacers to define a first opening; and

extending the first opening through said epitaxial layer of semiconductor material to form said opening.

12. The method of claim 1, further comprising forming sidewall spacers on side walls of the opening and before performing said steps of applying the anneal temperature.

13. The method of claim 1, wherein forming the transistor gate electrode comprises:

depositing a dielectric layer in the opening;

depositing a metal liner on the dielectric layer; and

filling said opening with a metal material.

14. The method of claim 1, wherein the steps of applying the anneal temperature comprise performing a laser annealing of the epitaxial regions and underlying portions of the semiconductor layer.

15-34. -34. (canceled)

35. A method, comprising:

growing an epitaxial layer of semiconductor material on a semiconductor substrate layer;

forming an opening in said epitaxial layer of semiconductor material to define a source epitaxial region and a drain epitaxial region separated by said opening, said source epitaxial region overlying a source substrate region of the semiconductor substrate layer and said drain epitaxial region overlying a drain substrate region of the semiconductor substrate layer;

simultaneously annealing both the source epitaxial region and source substrate region to combine the source epitaxial region and source substrate region into a transistor source region;

simultaneously annealing both the drain epitaxial region and drain substrate region to combine the drain epitaxial region and drain substrate region into a transistor drain region;

wherein a portion of the semiconductor substrate layer between the source and drain substrate regions forms a transistor channel region; and

forming a transistor gate electrode in said opening above the transistor channel region.

36. The method of claim 35, further comprising forming a substrate that includes the semiconductor substrate layer over a lower semiconductor layer with an insulating layer positioned between the semiconductor substrate layer and the lower semiconductor layer.

37. The method of claim 36, further comprising removing material of the insulating layer to form a cavity under at least the transistor channel region of the semiconductor substrate layer.

38. The method of claim 35, wherein said semiconductor substrate layer overlies an insulating layer, further comprising before forming the opening a step of removing material of the insulating layer to form a cavity under at least the transistor channel region of the semiconductor substrate layer.

39. The method of claim 35, wherein said semiconductor substrate layer overlies a substrate layer, further comprising removing material of the substrate layer to form a cavity under at least the transistor channel region of the semiconductor substrate layer.

40. The method of claim 35, wherein the steps of simultaneously annealing comprise performing a laser annealing.

41. The method of claim 35, wherein forming the opening comprises:

forming a dielectric layer over the epitaxial layer of semiconductor material;

forming a first opening extending through the dielectric layer;

forming sidewall spacers on side walls of the first opening to define a second opening; and

extending the second opening through said epitaxial layer of semiconductor material to form said opening.

42. The method of claim 35, wherein forming the opening comprises:

forming a sacrificial layer over the epitaxial layer of semiconductor material;

patterning the sacrificial layer to define a dummy gate;

forming sidewall spacers on side walls of the dummy gate;

removing the dummy gate between the sidewall spacers to define a first opening; and

extending the first opening through said epitaxial layer of semiconductor material to form said opening.

43. The method of claim 35, further comprising forming sidewall spacers on side walls of the opening and before performing said steps of simultaneously annealing.

44. The method of claim 35, wherein forming the transistor gate electrode comprises:

depositing a dielectric layer in the opening;

depositing a metal liner on the dielectric layer; and

filling said opening with a metal material.

45. A method, comprising:

growing an epitaxial layer of semiconductor material on a semiconductor substrate layer which overlies a sacrificial substrate layer supported by a substrate;

forming trench isolations in the semiconductor substrate layer to define an active region;

removing the sacrificial substrate layer within the active region to provide a cavity under the semiconductor substrate layer;

forming an opening in said epitaxial layer of semiconductor material to define a source epitaxial region and a drain epitaxial region separated by said opening, said source epitaxial region overlying a source substrate region of the semiconductor substrate layer and said drain epitaxial region overlying a drain substrate region of the semiconductor substrate layer;

annealing to combine both the source epitaxial region and source substrate region into a transistor source region over said cavity;

annealing to combine both the drain epitaxial region and drain substrate region into a transistor drain region over said cavity;

wherein a portion of the semiconductor substrate layer between the source and drain substrate regions forms a transistor channel region over said cavity; and

forming a transistor gate electrode in said opening above the transistor channel region.

46. The method of claim 45, wherein the sacrificial substrate layer is an insulating layer.

47. The method of claim 45, wherein the sacrificial substrate layer is a semiconductor layer.

48. The method of claim 45, wherein forming the opening comprises:

forming a dielectric layer over the epitaxial layer of semiconductor material;

forming a first opening extending through the dielectric layer;

forming sidewall spacers on side walls of the first opening to define a second opening; and

extending the second opening through said epitaxial layer of semiconductor material to form said opening.

49. The method of claim 45, wherein forming the opening comprises:

forming a sacrificial layer over the epitaxial layer of semiconductor material;

patterning the sacrificial layer to define a dummy gate;

forming sidewall spacers on side walls of the dummy gate;

removing the dummy gate between the sidewall spacers to define a first opening; and

extending the first opening through said epitaxial layer of semiconductor material to form said opening.

50. The method of claim 45, further comprising forming sidewall spacers on side walls of the opening and before performing said steps of annealing.

51. The method of claim 45, wherein forming the transistor gate electrode comprises:

depositing a dielectric layer in the opening;

depositing a metal liner on the dielectric layer; and

filling said opening with a metal material.