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NON-PLANAR SEMICONDUCTOR DEVICE HAVING OMEGA-FIN WITH DOPED SUB-FIN REGION AND METHOD TO FABRICATE SAME

  • US 20170069725A1
  • Filed: 06/26/2014
  • Published: 03/09/2017
  • Est. Priority Date: 06/26/2014
  • Status: Active Grant
First Claim
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1. A semiconductor device, comprising:

  • a plurality of semiconductor fins disposed above a semiconductor substrate, each semiconductor fin having a sub-fin portion below a protruding portion, the sub-fin portion narrower than the protruding portion;

    a solid state dopant source layer disposed above the semiconductor substrate, conformal with the sub-fin region but not the protruding portion of each of the plurality of semiconductor fins;

    an isolation layer disposed above the solid state dopant source layer and between the sub-fin regions of the plurality of semiconductor fins;

    a gate stack disposed above the isolation layer and conformal with the protruding portions of each of the plurality of semiconductor fins, the gate stack comprising a gate dielectric layer and gate electrode; and

    source and drain regions disposed in the protruding portions of each of the plurality of semiconductor fins, on either side of the gate stack.

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