NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME

• US 20170069731A1
• Filed: 02/01/2016
• Published: 03/09/2017
• Est. Priority Date: 09/04/2015
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: OH, Sung-Lae, KIM, Jin-Ho, SON, Chang-Man, LEE, Go-Hyun
• Granted Patent: US 9,653,562 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/41 of a memory region comprising a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region

Abstract

A nonvolatile memory device includes a pipe gate electrode layer formed over a substrate; a plurality of conductive layers stacked over the pipe gate electrode layer; source lines formed over an uppermost one of the conductive layers; first slits passing through the pipe gate electrode layer at positions overlapping with the source lines, and dividing the pipe gate electrode layer into a plurality of pipe gate electrodes, and second slits passing through the conductive layers at positions different from the first slits, and dividing the conductive layers into a plurality of memory blocks.

Claims

1. A nonvolatile memory device comprising:

a pipe gate electrode layer formed over a substrate;

a plurality of conductive layers stacked over the pipe gate electrode layer;

source lines formed over the plurality of conductive layers; and

first slits passing through the pipe gate electrode layer to divide the pipe gate electrode layer into a plurality of pipe gate electrodes,

wherein the first slits overlap with the source lines,

wherein second slits pass through the conductive layers to divide the conductive layers into a plurality of memory blocks, and

wherein the second slits do not overlap with the first slits.

2. The nonvolatile memory device according to claim 1, further comprising:

a circuit layer formed between the substrate and the pipe gate electrode layer.

3. The nonvolatile memory device according to claim 2,

wherein the circuit layer comprises a peripheral circuit for driving memory cells included in the plurality of memory blocks.

4. The nonvolatile memory device according to claim 2,

wherein the circuit layer comprises metal lines,

wherein the metal lines are electrically coupled to a voltage source, and

wherein the voltage source provides a common source voltage.

5. The nonvolatile memory device according to claim 4, further comprising;

a first dielectric layer filled in the first slits; and

contact plugs passing through the first dielectric layer and the conductive layers and electrically coupling the source lines to the metal lines.

6. The nonvolatile memory device according to claim 5, further comprising:

dielectric spacers extending from between the contact plugs and the first dielectric layer to between the contact plugs and the conductive layers.

7. The nonvolatile memory device according to claim 1,

wherein at least one uppermost conductive layer of the plurality of conductive layers becomes a select line, and the remaining conductive layers of the plurality of conductive layers become word lines.

8. The nonvolatile memory device according to claim 1, further comprising:

at least one pipe channel layer formed in each pipe gate electrode

a first vertical channel layer passing through the conductive layers, formed over the pipe channel layer, and coupled to the source line; and

a second vertical channel layer passing through the conductive layers, formed over the pipe channel layer, and coupled to a bit line.

9. The nonvolatile memory device according to claim 1,

wherein each of the plurality of pipe gate electrodes is disposed between two adjacent memory blocks and over a boundary region between the two adjacent memory blocks, and

wherein the plurality of pipe gate electrodes are isolated from each other by the first slits.

10. The nonvolatile memory device according to claim 9,

wherein each of the first slits is configured to divide the pipe gate electrode layer into a first pipe gate electrode and a second pipe gate electrode in each of the memory blocks.

11. The nonvolatile memory device according to claim 10, further comprising:

first pass transistors respectively corresponding to the plurality of memory blocks, wherein each of the first pass transistors is electrically coupled to first pipe gate electrodes, wherein each of the first pass transistors transfers a pipe gate voltage to the first pipe gate electrodes; and

second pass transistors respectively corresponding to the plurality of memory blocks, wherein each of the second pass transistors is electrically coupled between the first and the second pipe gate electrodes, wherein each of the second pass transistors transfers the pipe gate voltage applied to the first pipe gate electrode to the second pipe gate electrode

12. The nonvolatile memory device according to claim 9, further comprising:

discharge transistors respectively corresponding to the plurality of pipe gate electrodes, wherein each of the discharge transistors is coupled to each of the plurality of pipe gate electrodes, wherein each of the discharge transistors transfers a ground voltage to each of the plurality of pipe gate electrodes.

13. A method for manufacturing a nonvolatile memory device, comprising:

forming a pipe gate electrode layer over a substrate;

etching the pipe gate electrode layer to form first slits which divide the pipe gate electrode layer into a plurality of pipe gate electrodes;

forming a first dielectric layer filling the first slits;

forming a stack by alternately stacking a plurality of first material layers and a plurality of second material layers over the pipe gate electrodes and the first dielectric layer;

etching the first and second material layers by using the pipe gate electrodes as an etch stop layer to form second slits, wherein the second slits divide the stack into a plurality of memory blocks, wherein the second slits do not overlap with the first slits;

forming a second dielectric layer filling the second slits; and

forming source lines over the divided stack and over the second dielectric layer wherein the source lines overlap with the first slits.

14. The method according to claim 13, wherein the forming of the pipe gate electrode layer comprises:

forming a first pipe gate electrode layer over the substrate;

forming trenches in the first pipe gate electrode layer;

forming sacrificial layer patterns filling the trenches; and

forming a second pipe gate electrode layer over the first pipe gate electrode layer.

15. The method according to claim 14, further comprising:

after the forming of the stack and before the forming of the second slits,

etching the first and second material layers and the second pipe gate electrode layer to form vertical channel holes so that the vertical channel holes expose the sacrificial layer patterns;

removing the sacrificial layer patterns to form pipe channel holes so that the pipe channel holes communicate with the vertical channel holes;

forming a memory layer over internal surfaces of the pipe channel holes and the vertical channel holes; and

forming a channel layer over the memory layer.

18. The method according to claim 13,

wherein the first material layers comprise interlayer dielectric layers, and

wherein the second material layers comprise conductive layers.

19. The method according to claim 13, further comprising:

before the forming of the pipe gate electrode layer, forming a circuit layer over the substrate.

20. The method according to claim 19,

wherein the circuit layer comprises a peripheral circuit for driving memory cells of the plurality of memory blocks.

21. The method according to claim 19,

wherein the circuit layer comprises metal lines electrically coupled to a voltage source, and

wherein the voltage source provides a common source voltage.

22. The method according to claim 21, further comprising:

after the forming of the second slits and before the forming of the source lines,

removing the second material layers which are exposed by the second slits;

forming conductive layers in spaces which are created by removing the second material layers;

forming contact holes passing through the first material layers, the conductive layers, and the first dielectric layer under the source lines and exposing the metal lines of the circuit layer; and

forming contact plugs in the contact holes,

wherein the contact holes are coupled to the metal lines.

23. The method according to claim 22, further comprising:

after the forming of the contact holes and before the forming of the contact plugs,

forming dielectric spacers over sidewalls of the contact holes.

16. The method according to clam 13,

wherein the first material layers comprise interlayer dielectric layers, and the second material layers comprise sacrificial layers.

17. The method according to claim 16, further comprising:

after the forming of the second slits and before the forming of the source lines,

removing the second material layers which are exposed by the second slits; and

forming conductive layers in spaces which are created by removing the second material layers.