POWER SEMICONDUCTOR DEVICE

• US 20170069741A1
• Filed: 05/04/2016
• Published: 03/09/2017
• Est. Priority Date: 09/08/2015
• Status: Active Grant

• Current Assignee: Magnachip Semiconductor Limited (Magnachip Semiconductor)
• Original Assignee: Magnachip Semiconductor Limited (Magnachip Semiconductor)
• Inventors: NA, Kwang Ho, SONG, Seung Wook, KIM, Yong Hun
• Granted Patent: US 10,096,700 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Abstract

A power semiconductor device includes a semiconductor substrate, trench structures comprising a first, a second, a third and a fourth trench structure formed in the substrate, a second conductivity type body region formed between the trench structures, a first conductivity type source region formed in the second conductivity type body region, and an emitter electrode and a gate pad formed over the substrate, wherein each trench structure includes a top electrode and a bottom electrode, and each top electrode is insulated from the corresponding bottom electrode, and wherein the first trench structure is symmetric to the fourth trench structure, and the second trench structure is symmetric to the third trench structure, and wherein the first trench structure is not identical to the second trench structure, and wherein no first conductivity type source region is formed to be adjacent to the second trench structure and the third trench structure.

Claims

1. A power semiconductor device, comprising:

a semiconductor substrate;

trench structures comprising a first, a second, a third and a fourth trench structure formed in the substrate;

a second conductivity type body region formed between the trench structures;

a first conductivity type source region formed in the second conductivity type body region; and

an emitter electrode and a gate pad formed over the substrate,

wherein each trench structure comprises a top electrode and a bottom electrode, and each top electrode is insulated from a corresponding bottom electrode, and

wherein the first trench structure is symmetric to the fourth trench structure, and the second trench structure is symmetric to the third trench structure, and

wherein the first trench structure is different from the second trench structure, and

wherein no first conductivity type source region is formed to be adjacent to the second trench structure and the third trench structure.

2. The power semiconductor device of claim 1, wherein the top electrode and the bottom electrode of the first trench structure are connected to the gate pad and the emitter electrode, respectively, and

wherein the top electrode and the bottom electrode of the second trench structure are connected to the emitter electrode and the gate pad, respectively.

3. The power semiconductor device of claim 1, wherein the top electrode and the bottom electrode of the first trench structure are connected to the gate pad and the emitter electrode, respectively, and

wherein both the top electrode and the bottom electrode of the second trench structure are connected to the emitter electrode.

4. The power semiconductor device of claim 1, wherein the second conductivity type body region has a shallower depth than that of the top electrode of the trench structures with respect to the top surface of the substrate.

5. The power semiconductor device of claim 4, wherein the first conductivity type well region overlaps with both the top electrode and the bottom electrode of the trench structures.

6. The power semiconductor device of claim 4, wherein the first conductivity type well region has a higher impurity concentration than that of the first conductivity type drift region.

7. The power semiconductor device of claim 4, wherein the drift region comprises a first epitaxial layer and a second epitaxial layer, wherein the first epitaxial layer has a higher impurity concentration than that of the second epitaxial layer.

8. The power semiconductor device of claim 1, further comprising a first conductivity type drift region formed in the substrate, surrounding a bottom portion of the trench structure;

a first conductivity type well region formed over the first conductivity type drift region; and

a drain electrode formed on the bottom surface of the substrate.

9. The power semiconductor device of claim 1, wherein the top electrode has a smaller length than that of the bottom electrode.

10. The power semiconductor device of claim 1, wherein no channel region is formed in the body region adjacent to the second trench structure and the third trench structure.

11. A power semiconductor device, comprising:

a semiconductor substrate comprising first, second, third, and fourth trench structures, wherein

a second conductivity type body region is formed between each of the trench structures, wherein

a first conductivity type source region is formed in the second conductivity type body region, wherein no first conductivity type source region is formed to be adjacent to the second trench structure and the third trench structure,

wherein each trench structure comprises a top electrode and a bottom electrode, and wherein each top electrode is insulated from a corresponding bottom electrode.

12. The power semiconductor device of claim 11, further comprising an emitter electrode and a gate pad formed over the substrate.

13. The power semiconductor device of claim 12, wherein the top electrode and the bottom electrode of the first trench structure are connected to the gate pad and the emitter electrode, respectively, and

wherein the top electrode and the bottom electrode of the second trench structure are connected to the emitter electrode and the gate pad, respectively.

14. The power semiconductor device of claim 12, wherein the top electrode and the bottom electrode of the first trench structure are connected to the gate pad and the emitter electrode, respectively, and

wherein both the top electrode and the bottom electrode of the second trench structure are connected to the emitter electrode.

15. The power semiconductor device of claim 11, wherein the second conductivity type body region has a shallower depth than that of the top electrode of the trench structures with respect to the top surface of the substrate.

16. The power semiconductor device of claim 15, wherein the first conductivity type well region overlaps with both the top electrode and the bottom electrode of the trench structures.

17. The power semiconductor device of claim 15, wherein the first conductivity type well region has a higher impurity concentration than that of the first conductivity type drift region.

18. The power semiconductor device of claim 11, further comprising a first conductivity type drift region formed in the substrate, surrounding a bottom portion of the trench structure;

a first conductivity type well region formed over the first conductivity type drift region; and

a drain electrode formed on the bottom surface of the substrate.

19. The power semiconductor device of claim 11, wherein the top electrode has a smaller length than that of the bottom electrode.

20. The power semiconductor device of claim 11, wherein no channel region is formed in the body region adjacent to the second trench structure and the third trench structure.