SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

• US 20170069760A1
• Filed: 11/21/2016
• Published: 03/09/2017
• Est. Priority Date: 12/28/2010
• Status: Abandoned Application

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: YAMAZAKI, Shunpei
• Application Number:
  US15/357,045
• Publication Number:
  US 20170069760A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 21/426 using masks
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1229 with different crystal properties within a device or between different devices
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A semiconductor device in which fluctuation in electric characteristics due to miniaturization is less likely to be caused is provided. The semiconductor device includes an oxide semiconductor film including a first region, a pair of second regions in contact with side surfaces of the first region, and a pair of third regions in contact with side surfaces of the pair of second regions; a gate insulating film provided over the oxide semiconductor film; and a first electrode that is over the gate insulating film and overlaps with the first region. The first region is a CAAC oxide semiconductor region. The pair of second regions and the pair of third regions are each an amorphous oxide semiconductor region containing a dopant. The dopant concentration of the pair of third regions is higher than the dopant concentration of the pair of second regions.

Claims

1. (canceled)

2. A semiconductor device comprising:

an insulating film;

an oxide semiconductor film on the insulating film, the oxide semiconductor film comprising;

a first region;

a pair of second regions, the first region located between the pair of second regions; and

a pair of third regions, the first region and the pair of second regions located between the pair of third regions;

a gate insulating film over the oxide semiconductor film; and

a first electrode over the gate insulating film and overlapping with the first region,

wherein each of a crystallinity of the pair of second regions and a crystallinity of the pair of third regions is lower than a crystallinity of the first region.

3. The semiconductor device according to claim 2, further comprising:

a first sidewall insulating film and a second sidewall insulating film located on side surfaces of the first electrode,

wherein the first sidewall insulating film overlaps with one of the pair of second regions, and the second sidewall insulating film overlaps with the other of the pair of second regions.

4. The semiconductor device according to claim 2,

wherein the first region is a c-axis aligned crystal oxide semiconductor region.

5. The semiconductor device according to claim 2, further comprising:

a second electrode electrically connected to one of the pair of third regions; and

a third electrode electrically connected to the other of the pair of third regions.

6. The semiconductor device according to claim 5,

wherein the second electrode is in contact with a top surface of the one of the pair of third regions, and

wherein the third electrode is in contact with a top surface of the other of the pair of third regions.

7. The semiconductor device according to claim 5,

wherein the second electrode is in contact with a bottom surface of the one of the pair of third regions, and

wherein the third electrode is in contact with a bottom surface of the other of the pair of third regions.

8. The semiconductor device according to claim 2,

wherein the gate insulating film overlaps with the first region, the pair of second regions, and the pair of third regions.

9. The semiconductor device according to claim 2,

wherein the gate insulating film is an oxide insulating film.

10. The semiconductor device according to claim 2,

wherein the pair of second regions and the pair of third regions comprise one or more elements selected from nitrogen, phosphorus, and arsenic as the dopant, and

wherein the dopant concentration of the pair of second regions and the dopant concentration of the pair of third regions are higher than or equal to 5×

10¹⁸ atoms/cm³ and lower than or equal to 1×

10²² atoms/cm³.

11. The semiconductor device according to claim 2,

wherein the pair of second regions and the pair of third regions comprise one or more elements selected from nitrogen, phosphorus, and arsenic as the dopant,

wherein the dopant concentration of the pair of second regions is higher than or equal to 5×

10¹⁸ atoms/cm³ and lower than 5×

10¹⁹ atoms/cm³, and

wherein the dopant concentration of the pair of third regions is higher than or equal to 5×

10¹⁹ atoms/cm³ and lower than or equal to 1×

10²² atoms/cm³.

12. The semiconductor device according to claim 2,

wherein the oxide semiconductor film comprises two or more elements selected from In, Ga, Sn, and Zn.

13. A semiconductor device comprising:

a base insulating film;

an oxide semiconductor film on an insulating surface of the base insulating film, the oxide semiconductor film including a channel formation region and a pair of impurity regions with the channel formation region therebetween, wherein the oxide semiconductor film comprises indium and zinc;

a gate insulating film over the oxide semiconductor film;

a gate electrode over the channel formation region of the oxide semiconductor film with the gate insulating film interposed therebetween; and

first insulating films on side surfaces of the gate electrode, the first insulating films comprising silicon nitride,

wherein each of the pair of impurity regions comprises a first region and a second region, the first region being located between the channel formation region and the second region,

wherein the first regions of the pair of impurity regions are overlapped with the first insulating films while the second regions of the pair of impurity regions are not overlapped with the first insulating films, and

wherein the pair of impurity regions of the oxide semiconductor film contains nitrogen at a higher concentration than the channel formation region.

14. The semiconductor device according to claim 13,

wherein the channel formation region is a c-axis aligned crystal oxide semiconductor region.

15. The semiconductor device according to claim 13,

wherein the second region contains nitrogen at a higher concentration than the first region.

16. The semiconductor device according to claim 13, further comprising a second insulating film over the gate electrode,

wherein the second insulating film is in contact with the first insulating films and the second regions of the pair of impurity regions, and

wherein the second insulating film comprises a material selected from the group consisting of silicon oxide, silicon oxynitride, silicon nitride oxide, and silicon nitride.

17. The semiconductor device according to claim 13, further comprising a transistor having a channel formation region comprising single crystalline silicon, wherein the transistor is operationally connected to the oxide semiconductor film.

18. The semiconductor device according to claim 13,

wherein the oxide semiconductor film comprises In, Ga, and Zn.

19. The semiconductor device according to claim 13,

wherein a crystallinity of the pair of impurity regions is lower than a crystallinity of the channel formation region.

wherein a crystallinity of the pair of impurity regions is lower than a crystallinity of the channel formation region.