ATOMIC LAYER DEPOSITION SEALING INTEGRATION FOR NANOSHEET COMPLEMENTARY METAL OXIDE SEMICONDUCTOR WITH REPLACEMENT SPACER

• US 20170069763A1
• Filed: 09/04/2015
• Published: 03/09/2017
• Est. Priority Date: 09/04/2015
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Doris, Bruce B., Guillorn, Michael A., Lauer, Isaac, Miao, Xin
• Granted Patent: US 9,647,139 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/02603 Nanowires
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/78684 having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A semiconductor device including a gate structure present on at least two suspended channel structures, and a composite spacer present on sidewalls of the gate structure. The composite spacer may include a cladding spacer present along a cap portion of the gate structure, and an inner spacer along the channel portion of the gate structure between adjacent channel semiconductor layers of the suspended channel structures. The inner spacer may include a crescent shape with a substantially central seam.

Claims

1. A method of forming a semiconductor device comprising:

forming a gate structure on a stack of at least two semiconductor materials, wherein a spacer is present on sidewalls of the gate structure;

etching exposed portions of the stack of at least two semiconductor materials with an etch process, wherein the etch process includes a stage that removes one of the at least two semiconductor materials at a faster rate than a second of the at least two semiconductor materials to provide a divot region undercutting the spacer;

forming an atomic layer deposited (ALD) conformal dielectric layer that fills the divot region; and

forming epitaxial semiconductor material on remaining semiconductor material from said stack of at least two semiconductor materials.

2. The method of claim 1, wherein the etch process removes one the at least two semiconductor materials so that the remaining semiconductor material provides suspended source and drain semiconductor material layers.

3. The method of claim 2, wherein the epitaxial semiconductor material is formed on the suspended source and drain semiconductor material layers.

4. The method of claim 1, wherein the etching of the exposed portions of the stack of at least two semiconductor materials removes the entirety of the stack of the at least two semiconductor materials that extends beyond an outer sidewall of the spacer.

5. The method of claim 4, wherein said forming epitaxial semiconductor material on remaining semiconductor material from said stack of said at least two semiconductor materials comprises forming the epitaxial semiconductor material on an etched sidewall of the stack that is substantially aligned with the outer sidewall of the spacer.

6. The method of claim 1, wherein said forming the gate structure comprises forming a replacement gate structure on the stack of said at least two semiconductor materials prior to forming the atomic layer deposited conformal dielectric layer.

7. The method of claim 6 further comprising:

removing the replacement gate structure after said forming said epitaxial semiconductor material;

removing one of the two semiconductor materials of the stack in a channel region of the device;

converting a remaining semiconductor material of the stack in channel region to at least one of a nano-sheet or a nanowire geometry; and

forming a functional gate structure in an opening produced by said removing the replacement gate structure.

8. The method of claim 7, wherein the functional gate structure comprises a high-k gate dielectric and an atomic layer deposited metal gate conductor.

9. The method of claim 7 further comprising applying an etch process after said forming the ALD conformal dielectric layer to provide the exposed sidewalls of the remaining semiconductor material of the stack of two semiconductor materials.

10-15. -15. (canceled)

16. A semiconductor device comprising:

a gate structure present on at least two suspended channel structures;

a composite spacer present on sidewalls of the gate structure, the composite spacer comprising a cladding spacer present along a cap portion of the gate structure; and

an inner spacer along the channel portion of the gate structure between adjacent channel semiconductor layers of said at least two suspended channel structures, the inner spacer comprising a crescent shape with a substantially central seam.

17. The semiconductor device of claim 16, wherein the at least two suspended channel structures comprise nanowires, nanosheets or a combination thereof.

18. The semiconductor device of claim 17 further comprising source and drain regions comprising an epitaxial material abutting an outer sidewall of the composite spacer.

19. The semiconductor device of claim 16, wherein an apex of the crescent shape is positioned more proximate to a sidewall of the gate structure than the source and drain regions comprising the epitaxial material.

20. The semiconductor device of claim 16, wherein an apex of the crescent shape is positioned more proximate to the source and drain regions comprising the epitaxial material than a sidewall of the gate structure.