MEMORY SYSTEM

• US 20170075595A1
• Filed: 06/07/2016
• Published: 03/16/2017
• Est. Priority Date: 09/11/2015
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: MAEJIMA, Hiroshi
• Granted Patent: US 9,865,351 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 1/32 Means for saving power
• CPC Class Codes: G06F 11/00 Error detection; Error correction; Monitoring error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/0647 Migration mechanisms
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

A memory system includes a memory device including a memory cell array having a first region of multiple first memory cells and a second region of multiple second memory cells, first word lines each connected to a gate of one of the first memory cells, and second word lines each connected to a gate of one of the second memory cells, and a controller configured to control an operation of the memory device. The memory device selects one word line when reading from or writing to the first memory cells and selects more than one word line when reading from or writing to the second memory cells.

Claims

1. A memory system comprising:

a memory device that includes a memory cell array having a first region of multiple first memory cells and a second region of multiple second memory cells, first word lines each connected to a gate of one of the first memory cells, and second word lines each connected to a gate of one of the second memory cells; and

a controller configured to control an operation of the memory device,

wherein the memory device selects one word line when reading from or writing to the first memory cells and selects more than one word line when reading from or writing to the second memory cells.

2. The system according to claim 1, wherein the memory device selects two word lines when reading from or writing to the second memory cells.

3. The system according to claim 2, wherein the two word lines that are selected are adjacent word lines.

4. The system according to claim 1, wherein the first memory cells and the second memory cells are single-level cells and one page of data is read or written with the selection of one word line in the first region and the selection of more than word line in the second region.

5. The system according to claim 1, wherein the first memory cells and the second memory cells are multi-level cells and multiple pages of data are read or written with the selection of one word line in the first region and the selection of more than word line in the second region.

6. The system according to claim 1,

wherein the controller transmits a read or write command with a first control signal indicating that a read or write target is in the second region, and transmits the read or write command without the first control signal if the read or write target is in the first region.

7. The system according to claim 1,

wherein the second region stores information for controlling operations of the second memory cells.

8. The system according to claim 7, wherein the information for controlling operations of the second memory cells includes a read voltage and a shift read voltage to be used when read from the second memory cells and a programming voltage to be used when writing to the second memory cells.

9. The system according to claim 1, wherein the controller is configured to maintain access frequency information of a page of data stored in the first memory cells and to transfer the page of data stored in the first memory cells to the second memory cells based on the access frequency.

10. The system according to claim 9, wherein the controller instructs the memory device to transfer the page of data stored in the first memory cells to the second memory cells when the controller determines that the access frequency of the page of data is below a threshold.

11. The system according to claim 10, wherein the controller maps the page of data to an address within the second region upon receiving confirmation from the memory device that the transfer has completed.

12. A method of performing a reading operation in a memory device that includes a memory cell array having a first region of multiple first memory cells and a second region of multiple second memory cells, first word lines each connected to a gate of one of the first memory cells, and second word lines each connected to a gate of one of the second memory cells, said method comprising:

upon receiving a command to read from the first memory cells, selecting one word line and applying a first read voltage to the selected word line; and

upon receiving a command to read from the second memory cells, selecting more than word line and applying a second read voltage to the selected word lines.

13. The method according to claim 12, wherein two adjacent word lines are selected upon receiving the command to read from the second memory cells.

14. The method according to claim 12, wherein the first memory cells and the second memory cells are single-level cells and one page of data is read with the selection of one word line in the first region and the selection of more than word line in the second region.

15. The method according to claim 12, wherein the first memory cells and the second memory cells are multi-level cells and multiple pages of data are read with the selection of one word line in the first region and the selection of more than word line in the second region.

16. The method according to claim 12, further comprising:

reading the second region for information for controlling operations of the second memory cells, including the second read voltage.

17. A method of performing a writing operation in a memory device that includes a memory cell array having a first region of multiple first memory cells and a second region of multiple second memory cells, first word lines each connected to a gate of one of the first memory cells, and second word lines each connected to a gate of one of the second memory cells, said method comprising:

upon receiving a command to write to the first memory cells, selecting one word line and applying a first programming voltage to the selected word line; and

upon receiving a command to write to the second memory cells, selecting more than word line and applying a second programming voltage to the selected word lines.

18. The method according to claim 17, wherein two adjacent word lines are selected upon receiving the command to write to the second memory cells.

19. The method according to claim 17, wherein the first memory cells and the second memory cells are single-level cells and one page of data is written with the selection of one word line in the first region and the selection of more than word line in the second region.

20. The method according to claim 17, wherein the first memory cells and the second memory cells are multi-level cells and multiple pages of data are written with the selection of one word line in the first region and the selection of more than word line in the second region.