PRESERVING READ LOOK AHEAD DATA IN AUXILIARY LATCHES

• US 20170075629A1
• Filed: 10/30/2015
• Published: 03/16/2017
• Est. Priority Date: 09/11/2015
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Deshe, Noga, Kelner, Vered, Vishne, Gadi, Appel, Nurit, Manohar, Abhijeet, Tuers, Daniel E., Hahn, Judah Gamliel
• Granted Patent: US 10,025,532 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

A storage device utilizing read look ahead (RLA) may utilize auxiliary or spare latches as a RLA cache for storing pre-fetch data. The RLA may predict the next commands and do a speculative read to the flash using the latches for RLA storage. The auxiliary/spare latches may be present on a plane or die of non-volatile memory and may be different from the transfer data latch (XDL) that transfers data from the memory and the host. When the XDL is backed up, sense commands may still be performed and the data is stored in the auxiliary latches before being transferred with the XDL.

Claims

1. A method for pre-fetching data in a memory, the method comprising:

receiving an indication of data that may be subject to a pre-fetch;

storing the pre-fetch data in a latch;

waiting for a command for the pre-fetch data; and

execute command by moving the pre-fetch data from the latch.

2. The method of claim 1 wherein the latch comprises an auxiliary latch that is part of the memory.

3. The method of claim 2 wherein the pre-fetch data is moved to a transfer data latch (XDL).

4. The method of claim 3 wherein the XDL transfers the pre-fetch data to a host.

5. The method of claim 1 wherein the indication of data that may be subject to a pre-fetch comprises a prediction of which of the data may be requested next.

6. The method of claim 5 wherein the prediction may be based on a sequence of data already requested by a host.

7. The method of claim 1 wherein the memory comprises a flash memory and the flash memory comprises a three-dimensional (3D) memory configuration, and a controller is associated with operation of and storing to the flash memory.

8. A storage device comprising:

a memory comprising a plurality of die comprising memory blocks;

a plurality of latches on each of the die, wherein the latches comprise a transfer data latch (XDL) for transferring data and comprises one or more spare latches;

a sequential prediction circuitry that predicts requests from a host, wherein the prediction comprises identifying future read request and identifies pre-fetch data from the future read request; and

a pre-fetch data storage circuitry that uses the spare latches as a cache to store the pre-fetch data before transfer.

9. The storage device of claim 8 further comprising:

a controller coupled with the memory that is configured to communicate with the host for data transfer.

10. The storage device of claim 9 wherein the sequential prediction circuitry and/or the pre-fetch data storage circuitry are part of the controller.

11. The storage device of claim 9 wherein the memory comprises a three-dimensional (3D) memory configuration, and wherein the controller is associated with operation of and storing to the memory.

12. The storage device of claim 8 wherein the die comprise one or more planes, wherein the one or more planes each comprise one XDL and one or more spare latches.

13. The storage device of claim 8 wherein the pre-fetch data storage circuitry stores the pre-sense data in two or more of the spare latches in parallel.

14. The storage device of claim 8 wherein the read request comprises a sense and a transfer, wherein the pre-fetch data comprises information retrieved from the sense and the transfer comprises moving the pre-fetch data from the spare latch to the XDL.

15. A method for implementing read look ahead in a memory, the method comprising:

predicting future read requests;

fetching data for the predicted future read requests using a pre-sense operation;

storing the data for the predicted future read requests in one or more auxiliary latches; and

transferring, upon receipt of a read command, the data from the one or more auxiliary latches.

16. The method of claim 15 wherein the storing the data comprises parallel operations in which incoming pre-fetch data is stored in two or more of the auxiliary latches in parallel.

17. The method of claim 15 wherein the transferring comprises moving the data from the one or more auxiliary latches to a transfer data latch (XDL).

18. The method of claim 17 wherein the auxiliary latches comprise idle latches different from the XDL.

19. The method of claim 18 wherein the auxiliary latches comprise a read look ahead cache for temporarily storing the data from the pre-sense operation prior to the transferring.

20. The method of claim 18 wherein the predicting future read requests comprises identifying a sequence in the requested data.