DATA TRANSFER BUS COMMUNICATION USING SINGLE REQUEST TO PERFORM COMMAND AND RETURN DATA TO DESTINATION INDICATED IN CONTEXT TO ALLOW THREAD CONTEXT SWITCH

• US 20170075688A1
• Filed: 11/23/2016
• Published: 03/16/2017
• Est. Priority Date: 06/12/2000
• Status: Active Grant

• Current Assignee: ARM Finance Overseas Limited (SoftBank Group Corp.)
• Original Assignee: ARM Finance Overseas Limited (SoftBank Group Corp.)
• Inventors: Gelinas, Robert, Hays, W. Patrick, Katzman, Sol, Dally, William J.
• Granted Patent: US 11,226,820 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/30105 Register structure
• CPC Class Codes: G06F 9/30123 according to context, e.g. thread buffers
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/461 Saving or restoring of program or task context
• CPC Class Codes: G06F 9/48 Program initiating; Program switching, e.g. by interrupt
• CPC Class Codes: G06F 9/4881 Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues

Abstract

Systems and methods for managing context switches among threads in a processing system. A processor may perform a context switch between threads using separate context registers. A context switch allows a processor to switch from processing a thread that is waiting for data to one that is ready for additional processing. The processor includes control registers with entries which may indicate that an associated context is waiting for data from an external source.

Claims

1. (canceled)

2. A hardware register, comprising:

a first storage cell configured to indicate when a context is awaiting data from an external device;

a second storage cell configured to indicate when the context requires at least one of an external event and an external item of data to complete a task; and

a third storage cell configured to store an address of a register when the context is inactive and awaiting the data from the external device.

3. The hardware register of claim 2, wherein the first storage cell includes a bit indicative that the context is awaiting the data from the external device.

4. The hardware register of claim 2, further comprising a fourth storage cell configured to indicate that the context is available for execution.

5. The hardware register of claim 4, wherein the fourth storage cell comprises a flag indicative that the context is available for execution.

6. The hardware register of claim 2, wherein an address of the register indicates a location in which a result of an instruction of the context is stored.

7. The hardware register of claim 2, further comprising a context program counter configured to track a next instruction of the context to be executed.

8. A register file having a first hardware register comprising:

a first storage cell configured to indicate when a first context is awaiting data from an external device;

a second storage cell configured to indicate when the first context requires at least one of an external event and an external item of data to complete a task; and

a third storage cell configured to store an address of a register when the first context is inactive and awaiting the data from the external device.

9. The register file of claim 8, wherein the register file comprises a context program counter for tracking a next instruction of the first context to be executed.

10. The register file of claim 8 having a second hardware register comprising:

a fourth storage cell configured to indicate when a second context is awaiting data from an external device;

a fifth storage cell configured to indicate when the second context requires at least one of an external event and an external item of data to complete a task; and

a sixth storage cell configured to store an address of a register when the second context is inactive and awaiting the data from the external device.

11. The register file of claim 10, wherein the register file comprises a context program counter for tracking a next instruction of the second context to be executed.

12. A processor having a register file, the register file having a plurality of hardware registers, each hardware register comprising:

a first storage cell configured to indicate when a respective context is awaiting data from an external device;

a second storage cell configured to indicate when the respective context requires at least one of an external event and an external item of data to complete a task; and

a third storage cell configured to store an address of a register when the respective context is inactive and awaiting the external item of data.

13. The register file of claim 12, wherein the register file comprises a first program counter for tracking a next instruction of the respective contexts to be executed.

14. The processor of claim 13, further comprising a second program counter configured to point to the first program counter of an active context of the respective contexts.

15. The processor of claim 12, further comprising a bus and bus controller, wherein the processor is configured to send one or more instructions to an external device via the bus controller.

16. The processor of claim 15, wherein the bus controller is configured to add a first identifier to the one or more instructions to indicate an identity of the processor and an identity of the respective contexts.

17. The processor of claim 16, wherein the bus controller is configured to add a second identifier to the one or more instructions to indicate a function thereof.

18. The processor of claim 17, configured to set a flag in the first storage cell to indicate that the respective context is available for execution.