SEMICONDUCTOR DEVICE AND DISPLAY APPARATUS

• US 20170076662A1
• Filed: 12/17/2014
• Published: 03/16/2017
• Est. Priority Date: 03/06/2014
• Status: Active Grant

• Current Assignee: JDI Design and Development GK
• Original Assignee: JOLED Inc.
• Inventors: ISHII, Hiroaki
• Granted Patent: US 10,460,654 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2320/0252 Improving the response speed
• CPC Class Codes: G09G 2370/08 Details of image data interface between the display device controller and the data line driver circuit
• CPC Class Codes: G09G 2370/14 Use of low voltage differential signaling [LVDS] for display data communication
• CPC Class Codes: G09G 3/3225 using an active matrix
• CPC Class Codes: G09G 3/3266 Details of drivers for scan electrodes
• CPC Class Codes: G09G 3/3275 Details of drivers for data electrodes
• CPC Class Codes: G09G 5/006 Details of the interface to the display terminal specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04
• CPC Class Codes: G09G 5/12 Synchronisation between the display unit and other units, e.g. other display units, video-disc players

Abstract

A semiconductor device includes: a receiving circuit which receives communication frames each transmitted with a first period or a second period that are different from each other and including a synchronization code and data; a logic circuit which has a first operation state in which the received communication frames are each processed as data other than a digital video signal, and a second operation state in which the received communication frames are each processed as the digital video signal; a detecting circuit which detects the synchronization code from each of the received communication frames; a measuring circuit which measures a period of the detected synchronization code; and a determining circuit which determines the measured period. The logic circuit substantially makes a transition to the first operation state or the second operation state according to a result of the determining.

Claims

1. A semiconductor device which controls display of a display panel, the semiconductor device comprising:

a receiving circuit which receives a plurality of communication frames each transmitted with a first period or a second period and including a synchronization code and data, the first period and the second period being different from each other;

a logic circuit which has a first operation state in which the plurality of communication frames received by the receiving circuit are each processed as data other than a digital video signal, and a second operation state in which the plurality of communication frames received by the receiving circuit are each processed as the digital video signal;

a detecting circuit which detects the synchronization code from each of the plurality of communication frames received by the receiving circuit;

a measuring circuit which measures a period of the synchronization code detected in each of the plurality of communication frames; and

a determining circuit which determines whether the period measured is the first period or the second period, wherein

the logic circuit substantially makes a transition to the first operation state or the second operation state according to a result of the determining performed by the determining circuit.

2. The semiconductor device according to claim 1, wherein

the semiconductor device receives a notification from outside, the notification instructing a transition to the first operation state or a transition to the second operation state, and

the logic circuit

substantially makes the transition to the first operation state when the notification received last instructs the transition to the first operation state, and the result of the determining performed by the determining circuit indicates the first period, and

substantially makes the transition to the second operation state when the notification received last instructs the transition to the second operation state, and the result of the determining performed by the determining circuit indicates the second period.

3. The semiconductor device according claim 1, wherein

the logic circuit

discards the plurality of communication frames received by the receiving circuit when the notification received last instructs the transition to the first operation state, and the result of the determining performed by the determining circuit does not indicate the first period, and

discards the plurality of communication frames received by the receiving circuit when the notification received last instructs the transition to the second operation state, and the result of the determining performed by the determining circuit does not indicate the second period.

4. The semiconductor device according to claim 1, wherein

the semiconductor device controls (i) a row-drive circuit which drives the display panel including a plurality of pixels arranged in rows and columns, on a pixel-row basis, and (ii) a column-drive circuit which drives the display panel on a pixel-column basis.

5. The semiconductor device according to claim 1, wherein

the semiconductor device is a field programmable gate array (FPGA).

6. A display apparatus comprising:

a first semiconductor chip that is the semiconductor device according to claim 1;

a second semiconductor chip which transmits the plurality of communication frames unidirectionally to the first semiconductor chip;

a microcomputer which outputs a notification instructing a transition to the first operation state or a transition to the second operation state, to the first semiconductor chip and the second semiconductor chip;

a display panel including a plurality of pixels arranged in rows and columns;

a row-drive circuit which is controlled by the first semiconductor chip and drives a pixel row of the display panel; and

a column-drive circuit which is controlled by the first semiconductor chip and drives a pixel column of the display panel, wherein

the second semiconductor chip transmits the plurality of communication frames with the first period after receiving the notification instructing the transition to the first operation state, and transmits the plurality of communication frames with the second period after receiving the notification instructing the transition to the second operation state.

7. The display apparatus according to claim 6, wherein

the logic circuit

substantially makes the transition to the first operation state when the notification received last instructs the transition to the first operation state, and the result of the determining performed by the determining circuit indicates the first period, and

substantially makes the transition to the second operation state when the notification received last instructs the transition to the second operation state, and the result of the determining performed by the determining circuit indicates the second period.