Programming of Non-Volatile Memory Subjected to High Temperature Exposure

• US 20170076818A1
• Filed: 09/14/2016
• Published: 03/16/2017
• Est. Priority Date: 09/15/2015
• Status: Active Grant

• Current Assignee: Avalanche Technology Incorporated
• Original Assignee: Avalanche Technology Incorporated
• Inventors: Abedifard, Ebrahim, Chandrasekhar, Uday, Ranjan, Rajiv Yadav, Huai, Yiming
• Granted Patent: US 9,793,003 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 17/02 using magnetic or inductive elements G11C17/14 takes precedence
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/165 Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses digital stores using resistance random access memory elements G11C13/0002
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory

Abstract

A memory device having features of the present invention comprises a reprogrammable memory portion including therein a first plurality of magnetic tunnel junctions (MTJs) whose resistance is switchable; and a one-time-programmable (OTP) memory portion including therein a second plurality of MTJs whose resistance is switchable and a third plurality of MTJs whose resistance is fixed. Each MTJ of the first, second, and third plurality of MTJs includes a magnetic free layer having a magnetization direction substantially perpendicular to a layer plane thereof and a magnetic reference layer having a fixed magnetization direction substantially perpendicular to a layer plane thereof. The second plurality of MTJs represents one of two logical states and the third plurality of MTJs represents the other one of the two logical states.

Claims

1. A spin-transfer torque magnetic random access memory (STT-MRAM) device comprising:

a reprogrammable memory portion including therein a first plurality of magnetic tunnel junctions (MTJs) whose resistance is switchable; and

a one-time-programmable (OTP) memory portion including therein a second plurality of MTJs whose resistance is switchable and a third plurality of MTJs whose resistance is fixed,

wherein each MTJ of the first, second, and third plurality of MTJs includes a magnetic free layer having a magnetization direction substantially perpendicular to a layer plane thereof and a magnetic reference layer having a fixed magnetization direction substantially perpendicular to a layer plane thereof.

2. The STT-MRAM device of claim 1, wherein the magnetic free layer of each MTJ of the third plurality of MTJs is fixed.

3. The STT-MRAM device of claim 1, wherein the third plurality of MTJs are shorted.

4. The STT-MRAM device of claim 1, wherein each MTJ of the first and second plurality of MTJs is in either one of a low resistance state and a high resistance state and is switchable between the low and high resistance states.

5. The STT-MRAM device of claim 4, wherein each MTJ of the second plurality of MTJs is in the high resistance state.

6. The STT-MRAM device of claim 1, wherein the second plurality of MTJs represents one of two logical states and the third plurality of MTJs represents the other one of the two logical states.

7. A method for using a non-volatile memory including a plurality of memory cells, the method comprising the steps of:

storing data in the plurality of memory cells by shorting a portion of the plurality of memory cells to represent a first logical state while leaving the other portion of the plurality of memory cells to represent a second logical state; and

heating the plurality of memory cells to a temperature sufficiently high to cause at least one of the plurality of memory cells to change the resistance state thereof,

wherein a resistance state of each of the other portion of the plurality of memory cells is switchable between a low resistance level and a high resistance level.

8. The method of claim 7, wherein the temperature is between about 150°

C. and about 350°

C.

9. The method of claim 7, wherein the temperature is between about 200°

C. and about 300°

C.

10. The method of claim 7, wherein the non-volatile memory is spin-transfer torque magnetic random access memory (STT-MRAM).

11. The method of claim 10, wherein each of the plurality of memory cells includes a magnetic tunnel junction (MTJ).

12. The method of claim 11, wherein the MTJ includes a magnetic free layer having a magnetization direction substantially perpendicular to a layer plane thereof and a magnetic reference layer having a fixed magnetization direction substantially perpendicular to a layer plane thereof.

13. The method of claim 11, wherein each of the plurality of memory cells further includes a two-terminal selector device coupled to the MTJ in series.

14. The method of claim 7, wherein the step of storing data is carried out while the non-volatile memory is a part of a wafer before being diced.

15. The method of claim 7 further comprising the step of programming the other portion of the plurality of memory cells that represent the second logical state to the high resistance level after the step of heating.

16. The method of claim 15, wherein the step of programming the other portion of the plurality of memory cells is carried by out by exposing the non-volatile memory to an external magnetic field.

17. The method of claim 7 further comprising the step of updating the data stored in the plurality of memory cells after the step of heating and storing the updated data in another plurality of memory cells in the non-volatile memory, a resistance state of each of the another plurality of memory cells is switchable between a low resistance level and a high resistance level.

18. The method of claim 17, wherein the another plurality of memory cells replace the plurality of memory cells in the non-volatile memory device and have the same logical addresses as the plurality of memory cells.

19. The method of claim 17, wherein the low and high resistance levels of the another plurality of memory cells represent the first and second logical states, respectively.

20. The method of claim 17, wherein the low and high resistance levels of the another plurality of memory cells represent the second and first logical states, respectively.